Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate including a plurality of cell areas and a plurality of power areas such that each of the plurality of cell areas are alternately arranged with each of the plurality of power areas, in a second direction;   a plurality of gate structures extending in the second direction, each of the plurality of gate structures being spaced apart from each other in a first direction that is substantially perpendicular to the second direction;   a plurality of junction layers arranged at both sides of each of the plurality of gate structures and arranged in the second direction in such a configuration that each of the plurality of junction layer has a flat portion that is proximate to the power area; and   a plurality of cutting patterns arranged in the plurality of power areas and extending in the first direction such that each of the plurality of gate structures and each of the plurality of junction layers in neighboring cell areas of the plurality of cell areas are separated from each other by the cutting pattern.   
     
     
         2 . The semiconductor device of  claim 1 , wherein each oaf the plurality of junction layers includes an epitaxial layer grown in the second direction from a plurality of active fins extending in the first direction such that the epitaxial layer is largest around each of the plurality of power areas. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the epitaxial layer includes a point portion that is spaced apart horn each of the plurality of power areas. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a power rail extending in the first direction on the cutting pattern and to which a power signal is applied; and   a contact structure in contact with the power rail and the plurality of junction layers and configured to transfer the power signal to the plurality of junction layers from the power rail.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the contact structure includes:
 a cell contact that is in contact with the junction layer in the cell area: and a power contact arranged at a side of the cutting pattern, in contact with the flat portion of each of the plurality of junction layers and the power rail.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the cutting pattern includes a gate cutting pattern directly contacting each of the plurality of gate structures and having a first width, and a junction cutting, pattern that is spaced apart from the flat portion of each of the plurality of junction layers by a second contact bole and having a second width smaller than the first width, the gate cutting pattern and the junction cutting pattern being arranged alternately with each other in the first direction. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the power contact is arranged in the second contact hole such that a bottom surface of the power contact is in contact with a device isolation layer and a side surface of the power contact is in contact with the flat portion of each of the plurality of junction layers. 
     
     
         8 . The semiconductor device of  claim 1 , wherein each of the plurality of cell areas includes a PMOS area in which at least one p-type MOS transistor is arranged, an NMOS area in which at least one n-type MOS transistor is arranged, and a separation area interposed between the PMOS area and the NMOS area and separating the PMOS area and the NMOS area from each other, wherein the cutting pattern includes a nitride. 
     
     
         9 . The semiconductor device of  claim 8 , further comprising a separation pattern disposed on the separation area of each of the plurality of cell areas such that the plurality of gate structures and the plurality of junction layers in the NMOS area are separated from the plurality of gate structures and the plurality of junction layers in the PMOS area. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the separation pattern is arranged across at least one gate structure of the plurality of gate structures and at least one junction layer of the plurality of junction layers, in the first direction. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the separation pattern includes a same material as the cutting pattern. 
     
     
         12 . A method of manufacturing a semiconductor device, comprising:
 forming a plurality of active fins in at least a pair of cell areas extending in a first direction, the pair of cell areas being separated from each other by a power area;   forming a plurality of dummy gate structures and a plurality of gap fill patterns to a line shape extending in a second direction, substantially perpendicular to the first direction, such that each of the plurality of dummy gate structures and each of the plurality of gap fill patterns covers the plurality of active fins, alternately with respect to each other in the first direction, forming a cutting pattern in the power area in a line shape extending in the first direction such that the plurality of dummy gate structures and the plurality of gap fill patterns are separated from each other by a unit of a cell area of the at least the pair of cell areas; and   forming a junction layer in a gap space between neighboring dummy gate structures, of the plurality of dummy gate structures, such that the junction layer makes contact with the plurality of active fins in the at least the pair of cell areas and has a flat portion making contact with the cutting pattern.   
     
     
         13 . The method of  claim 12 , wherein forming the cutting pattern includes:
 partially removing each of the plurality of dummy gate structures, a gate spacer on side surfaces of each of the plurality of dummy gate structures and each of the plurality of gap fill patterns from the power area, thereby forming a cutting trench through which a device isolation layer is exposed;   forming a cutting layer on each of the plurality of dummy gate structures, the gate spacer and each of the plurality of gap fill patterns and the device isolation layer to a thickness for filling the cutting trench; and   planarizing the cutting layer until upper surfaces of each of the plurality of dummy gate structures, the gate spacer and each of the plurality of gap till patterns, so that the cutting layer remains exclusively in the cutting trench.   
     
     
         14 . The method of  claim 13 , wherein the cutting pattern includes silicon nitride (SiN), silicon oxynitride (SiON), and/or silicon carbon oxynitride (SiOCN). 
     
     
         15 . The method of  claim 13 , wherein forming the junction layer includes:
 removing each of the plurality of gap fill patterns from the at least the pair of cell areas, thereby forming an inter-spacer hole defined by neighboring gate spacers of the plurality of dummy gate structures and the cutting pattern and through which the plurality of active fins and the device isolation layer are exposed; and   conducting a selective epitaxial growth (SEG) process using the plurality of active fins as a seed such that the junction layer is horizontally grown to the cutting pattern in the second direction and is vertically grown along a side surface of the cutting pattern in a third direction substantially perpendicular to the first and the second directions to thereby form the flat portion making contact with the cutting pattern.   
     
     
         16 . The method of  claim 15 , wherein an upper portion of each of the plurality of active fins is removed from the inter-spacer hole in removing the gap fill pattern to thereby form an active recess in the inter-spacer hole, so that the junction layer is protruded into the active recess. 
     
     
         17 . The method of  claim 12 , further comprising:
 forming an insulation pattern at least partially covering the junction layer;   forming a gate trench extending in the second direction in the cell area by removing the plurality of dummy gate structures from the cell area;   forming a gate structure such that the gate trench is tilled with the gate structure;   forming a contact structure making contact with the junction layer; and   firming a power rail arranged on the cutting pattern and extending in the first direction such that the power rail makes contact with the contact structure.   
     
     
         18 . The method of  claim 17 , wherein forming the contact structure includes:
 forming a first interlayer dielectric pattern on each of the plurality of gate structures and the cutting pattern in a line extending in the second direction such that the insulation pattern and the cutting pattern are exposed through the first interlayer dielectric pattern;   removing the insulation pattern from the cell area, thereby forming a first contact hole through which the junction layer under the insulation pattern is exposed;   removing a peripheral portion of the cutting pattern from the power area, thereby forming a second pattern through which a device isolation layer under the cutting pattern and a side surface of the flat portion of the junction layer is exposed and a junction cutting pattern having a width smaller than that of the cutting pattern under the first interlayer dielectric pattern; and   forming a cell contact in the first contact hole and a power contact in the second contact hole such that the cell contact makes contact with the junction layer in the cell area and the power contact makes contact with the device isolation layer.   
     
     
         19 . The method of  claim 17 , further comprising, after forming the gate trench, forming a separation pattern for separating an NMOS transistor and a PMOS transistor on a separation area between an NMOS in which the NMOS transistors are arranged area and a PMOS area in which the PMOS transistors are arranged in the cell area. 
     
     
         20 . The method of clam  19 , wherein forming the separation pattern includes:
 forming an additional mask pattern on an entire surface of the substrate having the gate trench such that at least a portion of the separation area is exposed through the additional mask pattern;   forming a separation opening through which a device isolation layer surrounding the active fin is exposed by partially removing a gate spacer defining the gate trench and the insulation pattern at least partially covering the junction layer between the neighboring gate spacers, and   filling the separation opening with insulation materials.