Semiconductor device and manufacture thereof

Abstract

A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   at least one source region on the substrate;   a gate structure on the source region;   an interlayer dielectric layer around the gate structure, wherein the interlayer dielectric layer has a loss reduction region formed by conducting an ion implantation process comprising   
       silicon ion or carbon ion on the interlayer dielectric layer. 
     
     
         2 . The device of  claim 1 , wherein the gate structure comprises:
 a gate insulation layer on the source region;   a high-K dielectric layer on the gate insulation layer; and   a gate electrode on the high-K dielectric layer.   
     
     
         3 . The device of  claim 2 , wherein the upper surface of the interlayer dielectric layer is on substantially the same horizontal level as the upper surface of the gate electrode. 
     
     
         4 . The device of  claim 1 , wherein the interlayer dielectric layer comprises:
 a first insulation layer covering a portion of the source region; and   a second insulation layer on the first insulation layer.   
     
     
         5 . The device of  claim 1 , wherein the source region comprises:
 a first source region for a first device; and   a second source region for a second device.   
     
     
         6 . The device of  claim 2 , further comprising:
 a source electrode and a drain electrode in the source region and each at a side of the gate electrode; and   a spacer on the source region located between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.   
     
     
         7 . The device of  claim 6 , further comprising:
 a groove around the source region;   a third insulation layer at least partially filling the groove; and   a fourth insulation layer covering the third insulation layer, the source electrode, and the drain electrode, wherein the interlayer dielectric layer is formed on the fourth insulation layer.   
     
     
         8 . The device of  claim 1 , wherein the source region is a semiconductor fin or a source region for a planar semiconductor device.