Control of current collapse in thin patterned gan

Abstract

A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.

1 . A method of improving current collapse in a gallium nitride high electron mobility transistor, comprising:
 forming a recessed region in a surface of a substrate comprising a semiconductor material, wherein the recessed region exposes a first vertical sidewall of the substrate, a second vertical sidewall of the substrate, and a horizontal surface of the semiconductor material of the substrate;   forming a seed layer within the recessed region and directly on the horizontal surface of the semiconductor material of the substrate, wherein the seed layer extends continuously from the first vertical sidewall to the second vertical sidewall; and   forming a layered structure over the seed layer, the layered structure comprising at least a gallium nitride layer, wherein the gallium nitride layer is formed directly on the seed layer and extends continuously from, and is in direct contact with, the first vertical sidewall and the second vertical sidewall.   
     
     
         2 . The method of  claim 1 , wherein the layered structure has a thickness of at least 0.5 microns, a length of 1 to 200 microns, and a width of 1 to 200 microns. 
     
     
         3 . The method of  claim 2 , wherein the layered structure has a length of 10 to 50 microns and a width of 10 to 50 microns. 
     
     
         4 . The method of  claim 2 , wherein the layered structure has a thickness of at least 1 micron. 
     
     
         5 . The method of  claim 4 , wherein the layered structure has a thickness of 0.5 to 2.5 microns. 
     
     
         6 . The method of  claim 1 , wherein the recessed region is formed by etching the semiconductor material. 
     
     
         7 . The method of  claim 1 , wherein the recessed region has a depth of 0.6 to 3.5 microns, a length of 1 to 200 microns, and a width of 1 to 200 microns. 
     
     
         8 .- 9 . (canceled) 
     
     
         10 . The method of  claim 1 , wherein the seed layer and the gallium nitride layer have outermost sidewalls that are vertically aligned to each other. 
     
     
         11 . (canceled) 
     
     
         12 . A method of improving current collapse in a gallium nitride high electron mobility transistor, comprising:
 forming a recessed region in a surface of a substrate comprising a semiconductor material, wherein the recessed region exposes a first vertical sidewall of the substrate, a second vertical sidewall of the substrate, and a horizontal surface of the semiconductor material of the substrate;   forming a seed layer within the recessed region and directly on the horizontal surface of the semiconductor material of the substrate, wherein the seed layer extends continuously from the first vertical sidewall to the second vertical sidewalk, and   forming a layered structure over the seed layer, the layered structure comprising at least a gallium nitride layer and a buffer layer, wherein the buffer layer is located directly on the seed layer and extends continuously from, and is in direct contact with, the first vertical sidewall and the second vertical sidewall, and the gallium nitride layer is located directly on the buffer layer and extends continuously from, and is in direct contact with, the first vertical sidewall and the second vertical sidewall.   
     
     
         13 . The method of  claim 12 , wherein the seed layer, the buffer layer and the gallium nitride layer have outermost sidewalls that are vertically aligned to each other. 
     
     
         14 . The method of  claim 12 , wherein the buffer layer is composed of AlGaN and the gallium nitride layer is composed of carbon doped GaN. 
     
     
         15 . The method of  claim 1 , wherein the first and second vertical sidewalls include a dielectric material and a topmost semiconductor layer that are located above the semiconductor material of the substrate. 
     
     
         16 . The method of  claim 1 , wherein the forming of the seed layer comprises a selective deposition process. 
     
     
         17 . The method of  claim 1 , wherein the forming of the layered structure comprise a selective deposition process. 
     
     
         18 . The method of  claim 2 , wherein the layered structure has a current collapse of less than 10%. 
     
     
         19 .- 20 . (canceled)