Hybrid package
Abstract
A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.
Claims
exact text as granted — not AI-modified1 - 6 . (canceled)
7 . A device mounted on a printed circuit board, comprising:
an integrated circuit packaged as a Wafer Level Chip Scale Package (WLCSP),
wherein the WLCSP includes a plurality of solder balls on a bottom side;
an integrated circuit packaged as a Quad Flat Package (QFP), wherein the QFP includes a plurality of metal pins protruding from each of four sides;
wherein the QFP is mounted on a top side of the WLCSP and the QFP is affixed to the WLCSP using a layer of a thermal interface material; and
wherein protruding extreme tip of each of the plurality of metal pins is in a same plane as bottom extreme tip of each of the plurality of solder balls, wherein the protruding extreme tip and the plurality of solder balls are soldered to the printed circuit board.
8 . A hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) manufactured using an operation on a wafer, the operation comprising:
fabricating a strip including a plurality of flat packages attached to each other via metal pins; turning the strip upside down; applying a layer of a thermal interface material (TIM) on each of the flat packages
while the each of the flat packages is turned upside down;
mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, wherein a bottom side of the WLCSP includes a plurality of solder balls or solder pads;
curing the layer of the TIM;
singulating each of the flat packages by cutting the metal pins and bending the metal pins; and
soldering the plurality of solder balls and the metal pins directly to a printed circuit board.
9 . The hybrid package of claim 8 , wherein length of each of the metal pins is greater than height of the WLCSP.
10 . The hybrid package of claim 8 , wherein a protruding extreme tip of each of the mental pins is at a same plane as a bottom extreme tip of each of solder balls or solder pads.
11 . The hybrid package of claim 8 , wherein the layer of the TIM uses a material that provides a transfer of heat from the WLCSP to the flat package.
12 . The hybrid package of claim 8 , wherein the flat package is of type quad flat package (QFP).Join the waitlist — get patent alerts
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