Iq mismatch correction for zero-if/low-if tx/rx

Abstract

IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.

1 . A circuit to provide IQ mismatch correction for use in a system for radio frequency (RF) communication including a transmit (TX) end, and/or a receive (RX) end, the circuit comprising:
 at one of the TX end or the RX end, an analog signal chain and a digital signal chain:
 the analog signal chain including analog circuitry that introduces IQ mismatch signal impairments, 
 the digital signal chain including an IQmc mismatch corrector to filter In-phase and Quadrature digital signals to provide IQmc correction to correct the IQ mismatch impairments, and 
 an interface between the digital signal chain and the analog signal chain; and 
   the IQmc mismatch corrector, including:
 an I-path coupled to receive the In-phase digital signals (I signal), and 
 a Q-path coupled to receive the Quadrature digital signals (Q signal); and 
 an in-path filter element to filter either the I signal or the Q signal received in the same path, and 
 a cross-path filter element to filter either the I signal or the Q signal received in the other path. 
   
     
     
         2 . The circuit of  claim 1 , the IQmc mismatch corrector further including:
 an I-path delay element included in the I-path to provide a delay to the I signal corresponding to a delay through either the in-path filter element or the cross-path filter element; and   a Q-path delay element included in the Q-path to provide a delay to the Q signal corresponding to a delay through either the in-path filter element or the cross-path filter element.   
     
     
         3 . The circuit of  claim 1 , wherein
 the cross-path correction filter is connected from the Q-path to the I-path; and   the in-path correction filter is connected in the Q-path;   so that, the Q signal input is applied to the in-path and cross-path correction filters, and IQmc correction is provided for the I-path (Icorr) and the Q-path (Qcorr).   
     
     
         4 . The circuit of  claim 1 , wherein
 the cross-path correction filter is connected from the I-path to the Q-path; and   the in-path correction filter is connected in the I-path;   so that, the I signal input is applied to the in-path and cross-path correction filters, and IQmc correction is provided for the I-path (Icorr) and the Q-path (Qcorr).   
     
     
         5 . The circuit of  claim 1 , wherein
 the cross-path correction filter is connected from the I-path to the Q-path; and   the in-path correction filter is connected in the Q-path;   so that, the I signal input is applied to the cross-path correction filter, and the Q signal input is applied to the in-path correction filter, and IQmc correction is provided for the Q-path (Qcorr).   
     
     
         6 . The circuit of  claim 1 , wherein
 the cross-path correction filter is connected from the Q-path to the I-path; and   the in-path correction filter is connected in the I-path;   so that, the Q signal input is applied to the cross-path correction filter, and the I signal is applied to the in-path correction filter, and IQmc correction is provided for the I-path (Icorr).   
     
     
         7 . The circuit of  claim 1 , the IQmc mismatch corrector to provide IQmc correction that results in a change in linear response through the analog and digital signal chains, the circuit further comprising:
 in the analog signal chain, a digital step attenuator (DSA) to provide a selected DSA step attenuation;   in the digital signal chain,
 a DSA gain/phase correction block to provide a DSA correction signal to the DSA to correct the selected DSA step attenuation, and 
 a DSA gain/phase correction update module to adjust the DSA correction signal to compensate for the change in linear response. 
   
     
     
         8 . The circuit of  claim 1 , wherein
 the in-path and cross-path filter elements include filter coefficients selectively updated based on selectively estimated IQmc mismatch impairment; and   the in-path and cross-path filter elements are implemented in hardware, and the filter coefficients are selectively updated by computation in firmware based on estimated IQmc mismatch impairment.   
     
     
         9 . A transceiver circuit for transmitting and receiving radio frequency (RF) communication signals, including a transmit (TX) end, and a receive (RX) end, at the TX end and/or the RX end the circuit comprising:
 an analog signal chain, and including analog circuitry that introduces IQ mismatch signal impairments;   a digital signal chain including an IQmc mismatch corrector to filter In-phase and Quadrature digital signals to provide IQmc correction to correct the IQ mismatch impairments; and   an ADC (analog-to-digital conversion) circuitry to provide an interface between the analog signal chain and the digital signal chain;   the IQmc mismatch corrector including:
 an I-path coupled to receive the In-phase digital signals (I signal), and 
 a Q-path coupled to receive the Quadrature digital signals (Q signal); and 
 an in-path filter element to filter either the I signal or the Q signal received in the same path, and 
 a cross-path filter element to filter either the I signal or the Q signal received in the other path. 
   
     
     
         10 . The circuit of  claim 9 , the IQmc mismatch corrector further including:
 an I-path delay element included in the I-path to provide a delay to the I signal corresponding to a delay through either the in-path filter element or the cross-path filter element; and   a Q-path delay element included in the Q-path to provide a delay to the Q signal corresponding to a delay through either the in-path filter element or the cross-path filter element.   
     
     
         11 . The circuit of  claim 9 , wherein
 the cross-path correction filter is connected from the Q-path to the I-path; and   the in-path correction filter is connected in the Q-path;   so that, the Q signal input is applied to the in-path and cross-path correction filters, and IQmc correction is provided for the I-path (Icorr) and the Q-path (Qcorr).   
     
     
         12 . The circuit of  claim 9 , wherein
 the cross-path correction filter is connected from the I-path to the Q-path; and   the in-path correction filter is connected in the I-path;   so that, the I signal input is applied to the in-path and cross-path correction filters, and IQmc correction is provided for the I-path (Icorr) and the Q-path (Qcorr).   
     
     
         13 . The circuit of  claim 9 , wherein
 the cross-path correction filter is connected from the I-path to the Q-path; and   the in-path correction filter is connected in the Q-path;   so that, the I signal input is applied to the cross-path correction filter, and the Q signal input is applied to the in-path correction filter, and IQmc correction is provided for the Q-path (Qcorr).   
     
     
         14 . The circuit of  claim 9 , wherein
 the cross-path correction filter is connected from the Q-path to the I-path; and   the in-path correction filter is connected in the I-path;   so that, the Q signal input is applied to the cross-path correction filter, and the I signal is applied to the in-path correction filter, and IQmc correction is provided for the I-path (Icorr).   
     
     
         15 . The circuit of  claim 19 , the IQmc mismatch corrector to provide IQmc correction that results in a change in linear response through the analog and digital signal chains, the circuit further comprising:
 in the analog signal chain, a digital step attenuator (DSA) to provide a selected DSA step attenuation;   in the digital signal chain,
 a DSA gain/phase correction block to provide a DSA correction signal to the DSA to correct the selected DSA step attenuation, and 
 a DSA gain/phase correction update module to adjust the DSA correction signal to compensate for the change in linear response. 
   
     
     
         16 . The circuit of  claim 9 , wherein
 the in-path and cross-path filter elements include filter coefficients selectively updated based on selectively estimated IQmc mismatch impairment; and   the in-path and cross-path filter elements are implemented in hardware, and the filter coefficients are selectively updated by computation in firmware based on estimated IQmc mismatch impairment.   
     
     
         17 . A method to provide IQ mismatch correction, for use in a system for radio frequency (RF) communication, the method useable at a transmit (TX) end, and/or at a receive (RX) end in which an analog signal chain includes analog circuitry that introduces IQ mismatch signal impairments, the method comprising:
 digital filtering, in an IQmc corrector, In-phase and Quadrature digital signals to provide IQmc correction to correct the IQ mismatch impairments;   the digital filtering for IQmc correction accomplished by:
 receiving, in an I-path, the In-phase digital signals (I signal), and 
 receiving, in a Q-path, the Quadrature digital signals (Q signal), and 
 filtering in an in-path filter element either the I signal or the Q signal received in the same path, and 
 filtering in a cross-path filter element either the I signal or the Q signal received in the other path. 
   
     
     
         18 . The method of  claim 17 , the IQmc mismatch corrector further comprising:
 introducing a delay in the I-signal, with an I-path delay element included in the I-path, corresponding to a delay through either the in-path filter element or the cross-path filter element; and   introducing a delay in the Q-signal, with a delay element included in the Q-path, corresponding to a delay through either the in-path filter element or the cross-path filter element.   
     
     
         19 . The method of  claim 17 , wherein the IQmc mismatch corrector is configured with the in-path filter element and the cross-path filter element arranged so that either:
 the IQmc correction is provided for the I-path (Icorr) and the Q-path (Qcorr); or   the IQmc correction is provided for one of the I-path (Icorr) or the Q-path (Qcorr).   
     
     
         20 . The method of  claim 17 , wherein the analog signal chain includes a digital step attenuator (DSA) to provide a selected DSA step attenuation, the method further comprising;
 determining a change in linear response through the analog and digital signal chains that results from the digital filtering for IQmc correction; and   providing a correction signal to the DSA to adjust the selected DSA step attenuation to compensate for the change in linear response.   
     
     
         21 . The method of  claim 17 , wherein:
 the in-path and cross-path filter elements include filter coefficients selectively updated based on selectively estimated IQmc mismatch impairment; and   the in-path and cross-path filter elements are implemented in hardware, and the filter coefficients are selectively updated by computation in firmware based on estimated IQmc mismatch impairment.