Gate Stack Structure and Method for Forming the Same

Abstract

Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a field effect transistor including a gate stack, wherein the gate stack includes:
 a lanthanum doped high-k dielectric layer; 
 a work function layer over the lanthanum doped high-k dielectric layer; and 
 a gate electrode over the work function layer. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the lanthanum doped high-k dielectric layer includes at least one of HfO 2 , HfZrO, HfSiO, LaSiO, HfTaO, HfTiO, TiO, and Ta 2 O 5  doped with lanthanum. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the lanthanum doped high-k dielectric layer has a thickness in a range from 15 angstroms to 30 angstroms. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the field effect transistor is a p-type FinFET structure. 
     
     
         5 . The semiconductor device of  claim 1 , wherein an interface between the lanthanum doped high-k dielectric layer and the work function layer and an interface between the work function layer and the gate electrode have a lanthanum concentration less than 1.9×106 Counts-eV/s. 
     
     
         6 . The semiconductor device of  claim 1  further comprising an interfacial layer underlying the lanthanum doped high-k dielectric layer. 
     
     
         7 . A semiconductor device, comprising:
 a first interfacial layer over a substrate;   a first high-k dielectric layer over the first interfacial layer, the first interfacial layer and the first high-k dielectric layer sharing a first interface, wherein the first high-k dielectric layer comprises lanthanum, wherein the first high-k dielectric layer has a first lanthanum concentration less than 1.9×106 Counts-eV/s at the first interface;   a first work function layer over the first high-k dielectric layer, the first high-k dielectric layer and the first work function layer sharing a second interface; and   a first conductive material over the first work function layer.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the first high-k dielectric layer has a second lanthanum concentration less than 1.9×106 Counts-eV/s at the first interface. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the first high-k dielectric layer comprises lanthanum doped hafnium oxide. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the first high-k dielectric layer has a thickness in a range from 15 angstroms to 30 angstroms. 
     
     
         11 . The semiconductor device of  claim 7  further comprising first source/drain regions in the substrate on opposing sides of the first interfacial layer, wherein the first source/drain regions are p-type conductivity regions. 
     
     
         12 . The semiconductor device of  claim 11  further comprising:
 a second interfacial layer over the substrate; 
 a second high-k dielectric layer over the second interfacial layer, the second high-k dielectric layer being free of lanthanum; 
 a second work function layer over the second high-k dielectric layer; and 
 a second conductive material over the second work function layer. 
 
     
     
         13 . The semiconductor device of  claim 12 , wherein the first high-k dielectric layer and the second high-k dielectric layer comprise hafnium oxide. 
     
     
         14 . The semiconductor device of  claim 12  further comprising second source/drain regions in the substrate on opposing sides of the second interfacial layer, wherein the second source/drain regions are n-type conductivity regions. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the first work function layer and the second work function layer comprise a same material. 
     
     
         16 . A semiconductor device, comprising:
 a p-type transistor comprising:
 a first interfacial layer over a substrate; 
 a first high-k dielectric layer over and contacting the first interfacial layer, the first high-k dielectric layer having a first lanthanum concentration less than 1.9×106 Counts-eV/s adjacent the first interfacial layer; 
 a first work function layer over the first high-k dielectric layer, the first high-k dielectric layer having a second lanthanum concentration less than 1.9×106 Counts-eV/s adjacent the first work function layer; and 
 a first conductive material over the first work function layer; and 
   an n-type transistor comprising:
 a second interfacial layer over the substrate; 
 a second high-k dielectric layer over the second interfacial layer, the second high-k dielectric layer being free of lanthanum; 
 a second work function layer over the second high-k dielectric layer; and 
 a second conductive material over the second work function layer. 
   
     
     
         17 . The semiconductor device of  claim 16 , wherein the first high-k dielectric layer comprises lanthanum doped hafnium oxide. 
     
     
         18 . The semiconductor device of  claim 16 , wherein the first high-k dielectric layer has a thickness in a range from 15 angstroms to 30 angstroms. 
     
     
         19 . The semiconductor device of  claim 16 , wherein the first work function layer and the second work function layer comprise a same material. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the first work function layer and the second work function layer comprise different materials.