Substrates for iii-nitride epitaxy

Abstract

A wafer suitable for epitaxial growth of gallium nitride (GaN) in a Metal Oxide Chemical Vapor Deposition (MOCVD) process. The wafer includes a silicon substrate having a front side and a back side and an edge extending between the front side and the back side, the edge including a front bevel surface connected to the front side and a back bevel surface connected to the back side, wherein the silicon substrate comprises an oxygen denuded silicon layer surrounding a core. The wafer further includes a protection layer being a thermally grown silicon oxide (SiO 2 ) layer substantially covering the front bevel surface and the back bevel surface of the edge, while leaving at least a central region of the front side of the silicon substrate exposed, for preventing meltback during the MOCVD process.

What is claimed is: 
     
         1 . A wafer suitable for epitaxial growth of gallium nitride (GaN) in a Metal Oxide Chemical Vapor Deposition (MOCVD) process, said wafer comprising:
 a silicon substrate having a front side and a back side and an edge extending between said front side and said back side, said edge comprising a front bevel surface connected to said front side and a back bevel surface connected to said back side, wherein said silicon substrate comprises an oxygen denuded silicon layer surrounding a core; and   a protection layer being a thermally grown silicon oxide (SiO 2 ) layer substantially covering said front bevel surface and said back bevel surface of said edge, while leaving at least a central region of said front side of said silicon substrate exposed, for preventing meltback during said MOCVD process.   
     
     
         2 . A wafer according to  claim 1 , wherein said protection layer also covers said back side of said silicon substrate, such that only said central region is exposed. 
     
     
         3 . A wafer according to  claim 1 , further comprising a group-III nitride layer covering said central region. 
     
     
         4 . A wafer according to  claim 3 , wherein said group-III nitride layer comprises one of aluminium nitride, AlN, indium nitride, InN, gallium nitride, GaN, aluminium gallium nitride, AlGaN, indium aluminium nitride, InAlN, and indium aluminium gallium nitride, InAlGaN, or is formed from a stack of layers formed from any combination of these materials. 
     
     
         5 . A wafer according to  claim 1 , wherein said protection layer has a thickness greater than 100 nm, or in the range of 100 nm to 1000 nm, or in the range of 200 nm to 600 nm. 
     
     
         6 . A wafer according to  claim 1 , wherein said oxygen denuded silicon layer has a thickness in the range of 5 μm to 50 μm. 
     
     
         7 . A wafer according to  claim 1 , wherein said core has a precipitation size in the range of 2 nm to 20 nm. 
     
     
         8 . A wafer according to  claim 1 , further comprising a silicon nitride, SiN, layer covering said back side of said silicon substrate. 
     
     
         9 . A wafer according to  claim 1 , wherein said SiN layer covers said back bevel surface. 
     
     
         10 . A method of preparing a wafer suitable for epitaxial growth of gallium nitride in a Metal Oxide Chemical Vapor Deposition (MOCVD) process, said method comprising:
 providing a silicon substrate having a front side and a back side and an edge extending between said front side and said back side, said edge comprising a front bevel surface connected to said front side and a back bevel surface connected to said back side;   forming a protection layer being a thermally grown silicon oxide (SiO 2 ) layer covering said front bevel surface and said back bevel surface of said edge, while leaving at least a central region of said front side of said silicon substrate exposed; and   forming an oxygen denuded silicon layer surrounding a core in said substrate.   
     
     
         11 . A method according to  claim 10 , wherein said step of forming said protection layer comprises forming said protection layer such that it also covers said back side of said silicon substrate. 
     
     
         12 . A method according to  claim 10 , wherein said step of forming said protection layer comprises:
 performing a first oxidation of said silicon substrate to form a first oxide layer;   forming a silicon nitride, SiN, hard mask on said first oxide layer, wherein said hard mask covers said central region and does not cover said front bevel surface;   performing a second oxidation of said silicon substrate to form a second oxide layer being said protection layer, wherein said second oxide layer is grown on the substrate in regions not covered by said hard mask;   removing said hard mask from said first oxide layer in said central region; and   performing an oxide etch to remove said first oxide layer from said central region.   
     
     
         13 . A method according to  claim 12 , wherein said step of forming said SiN hard mask comprises:
 depositing a SiN layer on said first oxide layer;   coating said SiN layer with a resist;   developing said resist; and   performing a SiN etch to remove said SiN layer from an area not covered by said resist.   
     
     
         14 . A method according to  claim 12 , wherein said step of performing said second oxidation comprises growing said second oxide layer to have a thickness in the range of 100 nm to 1000 nm. 
     
     
         15 . A method according to  claim 12 , wherein said step of removing said SiN hard mask comprises performing a SiN etch down to said first oxide layer. 
     
     
         16 . A method according to  claim 12 , wherein said step of performing an oxide etch comprises a diluted hydrofluoric acid, HF, or buffered HF oxide etch step. 
     
     
         17 . A method according to  claim 10 , wherein said step of forming said protection layer comprises:
 providing an oxide layer covering said substrate;   coating said oxide layer with a resist;   developing said resist; and   performing an oxide etch to remove said oxide layer from said substrate in an area not covered by said resist to expose said central region.   
     
     
         18 . A method according to  claim 10 , wherein said method is performed in a standard Complementary Metal Oxide Semiconductor, CMOS, process. 
     
     
         19 . A method according to  claim 10 , further comprising annealing said substrate to grow said oxygen denuded silicon layer. 
     
     
         20 . A method according to  claim 19 , wherein said step of annealing comprises annealing at a temperature of 800 to 1,200° C. for a period of time such that said oxygen denuded silicon layer has a thickness in the range of 10 μm to 30 μm. 
     
     
         21 . A method according to  claim 19 , further comprising, after said step of annealing, reducing a temperature to between 600° C. and 800° C. to form precipitation seeds in said core of said substrate. 
     
     
         22 . A method according to  claim 10  used to prepare a wafer as claimed in  claim 1 .