Super-speed uart with per-frame bit-rate and independent variable upstream and downstream rates

Abstract

Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

What is claimed is: 
     
         1 . A clock generator comprising:
 an edge detection circuit configured to detect a first edge in a receive signal provided to a universal asynchronous receiver/transmitter (UART) receiver circuit, and a second edge in the receive signal; and   a delay-locked loop (DLL) configured to synchronize a sampling clock responsive to the first edge and the second edge,   wherein the sampling clock is used by the UART receiver circuit to capture data from the receive signal.   
     
     
         2 . The clock generator of  claim 1 , wherein the first edge comprises a negative-transitioning edge and the second edge comprises a positive-transitioning edge. 
     
     
         3 . The clock generator of  claim 1 , further comprising:
 a counter configured to count clock pulses in the sampling clock after the second edge, wherein the clock generator is disabled after a configured number of clock pulses have been transmitted in the sampling clock.   
     
     
         4 . The clock generator of  claim 1 , wherein the sampling clock has a period that is double a duration of time elapsed between the first edge and the second edge. 
     
     
         5 . The clock generator of  claim 1 , wherein the DLL is configured to synchronize the sampling clock for each data frame in the receive signal. 
     
     
         6 . The clock generator of  claim 5 , wherein each data frame includes 8 or more data bits. 
     
     
         7 . The clock generator of  claim 1 , wherein the DLL is configured to automatically determine baud rate of the receive signal based on synchronization signaling provided before each data frame in the receive signal, and wherein the synchronization signaling provides the first edge and the second edge. 
     
     
         8 . The clock generator of  claim 1 , wherein the DLL is configured to terminate an idle period after detecting the first edge. 
     
     
         9 . The clock generator of  claim 8 , wherein the DLL is further configured to synchronize the sampling clock to the second edge. 
     
     
         10 . The clock generator of  claim 1 , wherein the first edge and the second edge precede a start bit in the receive signal. 
     
     
         11 . A clock generator comprising:
 means for detecting edges in a receive signal provided to a universal asynchronous receiver/transmitter (UART), the edges including a first edge and a second edge; and   means for synchronizing a sampling clock using the first edge and the second edge,   wherein the sampling clock is used by a receiver circuit of the UART to capture data from the receive signal.   
     
     
         12 . The clock generator of  claim 11 , wherein the first edge comprises a negative-transitioning edge and the second edge comprises a positive-transitioning edge. 
     
     
         13 . The clock generator of  claim 11 , further comprising:
 means for counting clock pulses provided in the sampling clock after the second edge, wherein the clock generator is disabled after a configured number of clock pulses have been transmitted in the sampling clock.   
     
     
         14 . The clock generator of  claim 11 , wherein the sampling clock has a period that is double a duration of time elapsed between the first edge and the second edge. 
     
     
         15 . The clock generator of  claim 11 , wherein the means for synchronizing the sampling clock is configured to synchronize the sampling clock for each data frame in the receive signal. 
     
     
         16 . The clock generator of  claim 15 , wherein each data frame includes 8 or more data bits. 
     
     
         17 . The clock generator of  claim 11 , wherein the means for synchronizing the sampling clock is configured to automatically determine baud rate of the receive signal based on synchronization signaling provided before each data frame in the receive signal, and wherein the synchronization signaling provides the first edge and the second edge. 
     
     
         18 . The clock generator of  claim 11 , wherein the means for synchronizing the sampling clock is configured to terminate an idle period after detecting the first edge. 
     
     
         19 . The clock generator of  claim 18 , wherein the means for synchronizing the sampling clock is further configured to synchronize the sampling clock to the second edge. 
     
     
         20 . The clock generator of  claim 11 , wherein the first edge and the second edge precede a start bit in the receive signal.