Vertical memory devices

Abstract

A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.

1 .- 28 . (canceled) 
     
     
         29 . A vertical memory device, comprising:
 a channel structure including a lower channel structure and an upper channel structure sequentially stacked on an upper surface of a substrate in a first direction substantially perpendicular to the upper surface of the substrate; and   a gate electrode structure including a plurality of gate electrodes spaced apart from each other in the first direction, each of the plurality of gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate and surrounding a sidewall of the channel structure,   wherein the gate electrode structure includes at least one first gate electrode, a plurality of second gate electrodes, and at least one third gate electrode sequentially stacked on the upper surface of the substrate in the first direction, and   wherein the lower channel structure includes a doped semiconductor pattern, and first and second diffusion prevention patterns, the doped semiconductor pattern being adjacent to the first gate electrode, and the first and second diffusion prevention patterns covering lower and upper surfaces of the doped semiconductor pattern, respectively.   
     
     
         30 . The vertical memory device as claimed in  claim 29 , further comprising:
 a first undoped semiconductor pattern under the first diffusion prevention pattern; and   a second undoped semiconductor pattern on the second diffusion prevention pattern.   
     
     
         31 . The vertical memory device as claimed in  claim 29 , wherein:
 the lower channel structure fills a recess on the substrate and protrudes from the upper surface of the substrate, and   wherein a lower surface of the doped semiconductor pattern is lower than the upper surface of the substrate.   
     
     
         32 . The vertical memory device as claimed in  claim 31 , wherein an upper surface of the doped semiconductor pattern is higher than a lower surface of the first gate electrode and lower than an upper surface thereof. 
     
     
         33 . The vertical memory device as claimed in  claim 31 , wherein an upper surface of the doped semiconductor pattern is higher than or substantially coplanar with an upper surface of the first gate electrode. 
     
     
         34 . The vertical memory device as claimed in  claim 29 , wherein the doped semiconductor pattern includes a silicon pattern doped with boron, the first diffusion prevention pattern includes a semiconductor pattern doped with carbon, and the second diffusion prevention pattern includes a semiconductor pattern doped with carbon and boron. 
     
     
         35 . The vertical memory device as claimed in  claim 29 , further comprising an impurity layer at an upper surface of the substrate, the doped semiconductor pattern contacting the impurity layer. 
     
     
         36 . The vertical memory device as claimed in  claim 29 , wherein:
 the upper channel structure is on an upper central surface of the lower channel structure, and   the vertical memory device further comprises a charge storage structure extending from an upper edge surface of the lower channel structure in the first direction and surrounding an outer sidewall of the upper channel structure.   
     
     
         37 . The vertical memory device as claimed in  claim 29 , wherein the at least one first gate electrode includes a ground selection line (GSL), the plurality of second gate electrodes include word lines, and the at least one third gate electrode includes a string selection line (SSL). 
     
     
         38 .- 57 . (canceled)