Memory controller with memory resource memory management

Abstract

In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

What is claimed is: 
     
         1 . A memory controller communicatively coupleable to a memory resource having a plurality of memory resource regions being associated with a plurality of computing resources, the memory controller comprising:
 a memory resource interface to communicatively couple the memory controller to the memory resource;   a computing resource interface to communicatively couple the memory controller to the plurality of computing resources; and   a memory resource memory management unit to manage the memory resource.   
     
     
         2 . The memory controller of  claim 1 , wherein the memory resource memory management unit further comprises:
 a transaction module to manage transactions between the memory resource and the plurality of computing resources; and   a packet routing module to route packets between an appropriate one of the plurality of computing resources and a respective one of the plurality of memory resource regions associated with the appropriate one of the plurality of computing resources.   
     
     
         3 . The memory controller of  claim 1 , wherein memory resource regions not associated with a particular computing resource are inaccessible to the other computing resources. 
     
     
         4 . The memory controller of  claim 1 , wherein the computing resource is selected from the group consisting of at least one of a system on a chip, a field-programmable gate array, a digital signal processing unit, and a graphic processing unit. 
     
     
         5 . The memory controller of  claim 1 , wherein the memory resource memory management unit performs a memory address translation between a native memory address location of the computing resource and a physical memory address location of the memory resource. 
     
     
         6 . The memory controller of  claim 1 , wherein at least one of the plurality of computing resources further comprises:
 a native memory management unit to manage a native memory on the computing resource.   
     
     
         7 . The memory controller of  claim 6 , wherein the at least one of the plurality of computing resources further comprises:
 a processing resource to execute instructions on the computing resource and to read data from and write data to the memory resource region of the memory resource associated with the computing resource via at least one of the plurality of memory controllers.   
     
     
         8 . A computing system comprising:
 a memory resource further comprising a plurality of memory resource regions;   a plurality of computing resources, each of the plurality of computing resources being associated with one of the plurality of memory resource regions of the memory resource; and   a plurality of memory controllers, each memory controller further comprising:
 a memory resource interface to communicatively couple the memory controller to the memory resource, 
 a computing resource interface to communicatively couple the memory controller to the plurality of computing resources, and 
 a memory resource memory management unit to manage the memory resource region of the memory resource associated with each of the plurality of computing resources. 
   
     
     
         9 . The computing system of  claim 8 , wherein at least one of the plurality of computing resources further comprises:
 a native memory management unit to manage a native memory on the computing resource; and   a processing resource to execute instructions on the computing resource and to read data from and write data to the memory resource region of the memory resource associated with the computing resource via at least one of the plurality of memory controllers.   
     
     
         10 . The computing system of  claim 8 , wherein the memory resource memory management unit performs a memory address translation between a native memory address location of the computing resource and a physical memory address location of the memory resource. 
     
     
         11 . The computing system of  claim 8 , wherein the plurality of memory controllers and the plurality of computing resources are communicatively coupleable in a mesh configuration. 
     
     
         12 . The computing system of  claim 8 , wherein memory resource regions not associated with a particular computing resource are inaccessible to the other computing resources. 
     
     
         13 . A method comprising:
 receiving, through a computing resource interface of a memory controller, at least one of a data read request to read data from a memory resource communicatively coupleable to the memory controller and a data write request to write data to the memory resource;   translating, by a memory resource memory management unit of the memory controller, the at least one of the data read request and the data write request between a native memory address location of the computing resource and a physical memory address location of the memory resource; and   performing, by the computing resource, the at least one of the data read request and the data write request.   
     
     
         14 . The method of  claim 13 , wherein the physical memory address location is located in a region of the memory resource associated with the computing resource. 
     
     
         15 . The method of  claim 13 , wherein the native memory address location is at least one of a native physical address location and a native virtual memory address location.