Multiple display synchronization

Abstract

A device includes a plurality of display panels, a plurality of display controllers, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing indication, and a processor coupled to the plurality of display controllers to receive the timing indications from the plurality of display controllers. Each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel. The processor is configured to delay a refresh of the plurality of display panels until the timing indication is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels.

What is claimed is: 
     
         1 . A device comprising:
 a plurality of display panels;   a plurality of display controllers, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing indication; and   a processor coupled to the plurality of display controllers to receive the timing indications from the plurality of display controllers;   wherein each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel, and   wherein the processor is configured to delay a refresh of the plurality of display panels until the timing indication is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels.   
     
     
         2 . The device of  claim 1 , wherein the processor is configured to send a refresh instruction to each display controller of the plurality of display controllers upon receipt of the timing indication from each respective display controller of the plurality of display controllers. 
     
     
         3 . The device of  claim 2 , wherein:
 the processor is configured to generate image data to be rendered on the plurality of display panels; and   the processor is configured to send the refresh instruction via a command interface between the processor and the respective display controller.   
     
     
         4 . The device of  claim 1 , wherein the processor is configured to send a refresh trigger signal to each display controller of the plurality of display controllers upon receipt of the timing indication from each respective display controller of the plurality of display controllers. 
     
     
         5 . The device of  claim 4 , wherein:
 the timing indication is provided as a timing signal; and   the processor comprises a signal processor configured to implement an AND operation on the timing signals generated by the plurality of display controllers.   
     
     
         6 . The device of  claim 5 , further comprising an application processor configured to generate image data to be rendered on the plurality of display panels of the device, wherein the signal processor is configured to synchronize the plurality of display panels when the application processor is not generating the image data. 
     
     
         7 . The device of  claim 6 , wherein the application processor is further configured to provide an enable signal to each display controller of the plurality of display controllers to control whether the plurality of display controllers are responsive to an output from the signal processor indicative of the AND operation. 
     
     
         8 . The device of  claim 5 , wherein one of the plurality of display controllers comprises the signal processor. 
     
     
         9 . The device of  claim 5 , wherein the signal processor comprises a counter, the counter being configured to track a time elapsed since a last refresh. 
     
     
         10 . The device of  claim 1 , wherein:
 each display controller of the plurality of display controllers is configured to receive image data via an image data interface; and   each timing indication is provided as a respective timing signal on a respective dedicated line separate from the image data interface.   
     
     
         11 . A device comprising:
 a plurality of display panels;   a processor configured to generate image data for rendering on a plurality of display panels of the device;   a plurality of display controllers coupled to the processor to receive the image data, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels of the device, each respective display controller of the plurality of display controllers being configured to generate a timing signal; and   a signal processor configured to receive the timing signals from the plurality of display controllers;   wherein each timing signal is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel,   wherein the signal processor is configured to generate a trigger signal once the timing signal is received from each respective display controller of the plurality of display controllers, and   wherein the trigger signal is used by the plurality of display controllers to synchronize a refresh of the plurality of display panels.   
     
     
         12 . The device of  claim 11 , wherein the signal processor is enabled to control the plurality of display controllers when the plurality of display controllers are operating in a panel self-refresh mode of operation. 
     
     
         13 . The device of  claim 11 , wherein the signal processor is configured to provide a collective timing signal to the processor indicative of whether the timing signals have been received from each display controller of the plurality of timing controllers. 
     
     
         14 . The device of  claim 11 , wherein the signal processor comprises an AND gate configured to implement an AND operation on the timing signals generated by the plurality of display controllers. 
     
     
         15 . The device of  claim 11 , wherein the signal processor is configured as a state machine, the state machine comprising a counter configured to track a time elapsed since a last refresh. 
     
     
         16 . A method of synchronizing a plurality of display panels of a device, the method comprising:
 detecting, with a processor, a plurality of timing indications, each timing indication of the plurality of timing indications being generated by a respective display controller of a plurality of display controllers, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, wherein each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel; and   directing, with the processor, the plurality of display controllers to refresh the plurality of display panels once the timing indication from each respective display controller of the plurality of display controllers is detected to synchronize the plurality of display panels.   
     
     
         17 . The method of  claim 16 , further comprising generating, with the processor, image data to be rendered on the plurality of display panels, wherein directing the plurality of display controllers comprises sending a refresh instruction from the processor via a command interface between the processor and the respective display controller. 
     
     
         18 . The method of  claim 16 , further comprising sending an enable signal from an application processor of the device to enable the processor to direct the plurality of display controllers. 
     
     
         19 . The method of  claim 16 , wherein directing the plurality of display controllers comprises generating, with the processor, a trigger signal via an AND operation of the processor. 
     
     
         20 . The method of  claim 16 , wherein detecting the plurality of timing indications comprises monitoring a respective dedicated line separate from an image data interface via which the plurality of display controllers are configured to receive image data.