Method of forming a semiconductor device termination and structure therefor

Abstract

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

1 - 12 . (canceled) 
     
     
         13 . The method according to  claim 23 , including forming the second layer and the third layer from a common layer. 
     
     
         14 . The method according to  claim 13 , further comprising forming a separator layer between the first layer and the second layer wherein the separator layer is at least one of an intrinsic layer or a dielectric layer. 
     
     
         15 - 17 . (canceled) 
     
     
         18 . A method of forming a semiconductor edge termination structure of a semiconductor device in a trench comprising the steps of:
 forming the semiconductor device to include an active region and an edge termination area wherein the edge termination area is external to the active region and is positioned between the active region and an edge of the semiconductor device including forming the edge termination structure within the edge termination area;   forming the trench in a semiconductor layer of a first conductivity type wherein the semiconductor layer overlies the semiconductor substrate including forming the trench in the edge termination area;   forming a first layer having a portion that is adjacent to and substantially parallel to sidewalls of the trench;   forming a second layer having a portion that is adjacent to and substantially parallel to the portion of the first layer, wherein a conductivity type of the second layer is different than a conductivity type of the first layer;   forming a buffer region adjacent to a sidewall of the second layer wherein the buffer region has a sidewall that extends into the trench and wherein the second layer is adjacent an entire length of the sidewall of the buffer region; and   forming a dielectric layer on and in direct contact with a surface of the first layer.   
     
     
         19 . The method according to  claim 18 , including forming the first layer as an N-type layer. 
     
     
         20 . The method according to  claim 18 , including forming the termination structure as a portion of the semiconductor device, wherein the termination area includes at least one of a junction termination extension, a Field-Plate, and one or more P+ rings, and wherein the semiconductor device is one of an IGBT, a Junction-Schottky diode, an SOI device, and a Thyristor. 
     
     
         21 . The method of  claim 18  including forming at least one P+ ring in a portion of the semiconductor layer that is within the termination area wherein the P+ ring is spaced apart from the edge termination structure. 
     
     
         22 . The method of  claim 18  including forming the buffer region in direct contact with the sidewall of the second layer. 
     
     
         23 . The method of  claim 18  including forming a third layer overlying the buffer region, wherein a conductivity type of the third layer is the same as the conductivity type of the second layer. 
     
     
         24 . The method of  claim 23  including forming the dielectric layer on and in direct contact with a surface of the third layer. 
     
     
         25 - 27 . (canceled) 
     
     
         28 . the method of  claim 18  including forming the dielectric layer to extend to be on and in direct contact with the second layer. 
     
     
         29 . the method of  claim 18  including forming the buffer region having a length that extends in a first direction away from a surface of the first layer toward the substrate and having a width along the length wherein the buffer region does not extend laterally in a second direction for a second distance that is greater than the width.