Semiconductor package and manufacturing process

Abstract

A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

1 . A semiconductor package, comprising:
 a base material having a top surface and an inner lateral surface;   a capture land disposed in or on the base material, and having an outer side surface;   an interconnection structure disposed along the inner lateral surface of the base material, and on the capture land, wherein the interconnection structure has an outer side surface, and an outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure;   a semiconductor chip disposed on the top surface of the base material; and   an encapsulant disposed adjacent to the top surface of the base material, and covering the semiconductor chip.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the interconnection structure contacts the capture land, and the outer side surface of the interconnection structure is substantially coplanar with the outer side surface of the capture land. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the encapsulant has an outer side surface, and the outer side surface of the encapsulant is substantially coplanar with the outer side surface of the capture land. 
     
     
         4 . The semiconductor package of  claim 1 , further comprising an indentation structure defined by the inner lateral surface of the base material and the capture land. 
     
     
         5 . The semiconductor package of  claim 4 , wherein at least a portion of the interconnection structure is disposed within the indentation structure. 
     
     
         6 . The semiconductor package of  claim 4 , wherein the inner lateral surface of the base material is inclined with respect to the top surface of the base material. 
     
     
         7 . The semiconductor package of  claim 4 , wherein the base material includes a first sub-base material and a second sub-base material, the indentation structure is defined by an inner lateral surface of the first sub-dielectric layer and the capture land. 
     
     
         8 . The semiconductor package of  claim 4 , wherein the indentation structure includes a first portion disposed adjacent to the capture land and a second portion disposed away from the capture land, and a width of the first portion is less than a width of the second portion. 
     
     
         9 . The semiconductor package of  claim 4 , wherein a width of the capture land is greater than a width of the indentation structure. 
     
     
         10 . The semiconductor package of  claim 4 , wherein the base material includes at least one dielectric structure and at least one circuitry structure, and a portion of the dielectric structure and a portion of the circuitry structure are disposed above the indentation structure. 
     
     
         11 . The semiconductor package of  claim 10 , wherein the base material further includes a via structure disposed above the indentation structure, and the via structure connects the circuitry structure and the capture land. 
     
     
         12 . The semiconductor package of  claim 1 , wherein the capture land is a via stop structure. 
     
     
         13 . The semiconductor package of  claim 12 , wherein the via stop structure is a laser drilling stop structure or etching stop structure. 
     
     
         14 . The semiconductor package of  claim 1 , wherein the base material includes at least one dielectric structure and at least one circuitry structure, and the capture land is a portion of a circuitry structure. 
     
     
         15 . A semiconductor package, comprising
 a substrate, including:
 a base material having a top surface and an outer side surface connected to the top surface;
 an indentation structure recessed from the outer side surface of the base material, and having a first width; 
 
 a capture land disposed in or on the base material and disposed adjacent to the indentation structure, wherein the capture land has a third width that is greater than the first width of the indentation structure; and 
 an interconnection structure disposed in the indentation structure and connected to the capture land; 
   a semiconductor chip disposed adjacent to the top surface of the base material; and   an encapsulant covering the semiconductor chip and the substrate.   
     
     
         16 . The semiconductor package of  claim 15 , wherein the base material of the substrate includes a circuitry structure connected to the capture land by a via structure. 
     
     
         17 . The semiconductor package of  claim 15 , wherein the encapsulant has an outer side surface, and the outer side surface of the encapsulant is substantially coplanar with the outer side surface of the base material of the substrate. 
     
     
         18 . The semiconductor package of  claim 15 , wherein the base material further has an inner lateral surface, and the indentation structure is defined by the inner lateral surface of the base material and the capture land. 
     
     
         19 . The semiconductor package of  claim 15 , wherein an outer side surface of the substrate includes the outer side surface of the base material, an outer side surface of the interconnection structure and an outer side surface of the capture land. 
     
     
         20 . The semiconductor package of  claim 15 , wherein the capture land is a via stop structure. 
     
     
         21 . The semiconductor package of  claim 20 , wherein the via stop structure is a laser drilling stop structure or etching stop structure. 
     
     
         22 - 27 . (canceled)