Semiconductor structures having low resistance paths throughout a wafer

Abstract

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

What is claimed is: 
     
         1 . A method, comprising:
 forming a silicide layer on a substrate;   forming an interlevel dielectric material over the silicide layer;   forming one or more metal wiring and interconnects in the interlevel dielectric material; and   forming a plurality of devices in direct contact with the silicide layer,   wherein the silicide layer extends between the devices such that sides of the devices are in direct contact with the silicide layer and the interlevel dielectric material, and a center of the devices is below the one or more metal wiring and interconnects such that the devices are electrically isolated from the one or more metal wiring and interconnects.   
     
     
         2 . The method of  claim 1 , further comprising forming a seed and barrier layer on a upper surface of the interlevel dielectric material. 
     
     
         3 . The method of  claim 2 , wherein the seed and barrier layer contact a surface of the one or more metal wiring and interconnects. 
     
     
         4 . The method of  claim 3 , wherein the seed and barrier layer contacts a conductive material of the metal wiring and interconnects. 
     
     
         5 . The method of  claim 4 , further comprising:
 removing exposed portions of the seed layer and barrier layer by a wet etch process to expose the one or more metal wiring and interconnects; and   forming a metal wiring over the exposed one or more metal wiring and interconnects.   
     
     
         6 . The method of  claim 5 , wherein the metal wiring is formed by depositing and patterning a resist on the interlevel dielectric material and over the seed layer and barrier layer, patterning the resist to form openings and depositing metal material in the openings. 
     
     
         7 . The method of  claim 6 , wherein the depositing metal material in the openings is an electroplating process. 
     
     
         8 . The method of  claim 7 , wherein after formation of the metal wiring, the resist is removed. 
     
     
         9 . The method of  claim 1 , wherein the one or more metal wiring and interconnects are separated from the silicide layer by a portion of the interlevel dielectric material. 
     
     
         10 . The method of  claim 1 , wherein a bottom surface of the one or more metal wiring and interconnects is covered by the interlevel dielectric material. 
     
     
         11 . The method of  claim 1 , wherein a bottom surface of the one or more metal wiring and interconnects is covered by the interlevel dielectric material. 
     
     
         12 . A structure, comprising:
 a plurality of devices over a substrate;   a silicide layer over the substrate and extending between the devices such that sides of the devices are in direct contact with the silicide layer;   an interlevel dielectric material over the devices; and   forming one or more metal wiring and interconnects in the interlevel dielectric material.