Power density matching circuits for power amplifiers

Abstract

Circuits and methods related to power amplifiers. Power density matching circuits can be provided to match power densities in reference devices and amplifying devices. In some implementations, a power density matching circuit includes a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between a power supply node and ground and a second transistor and a fourth transistor coupled emitter to collector between the power supply node and ground. The transistors of the current translator can be sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor. The current translation can provide power density matching between the amplifying transistor and the reference transistor.

What is claimed is: 
     
         1 . A power density matching circuit configured to match power density changes between an amplifying transistor and a reference transistor, the circuit comprising:
 a supply node configured to receive a supply voltage;   a differential node configured to receive a signal from a differential amplifier;   a reference node configured to provide a bias signal to the reference transistor;   an amplifying node configured to provide a bias signal to the amplifying transistor; and   a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.   
     
     
         2 . The power density matching circuit of  claim 1  wherein temperature independent current translation provides power density matching between the amplifying transistor and the reference transistor. 
     
     
         3 . The power density matching circuit of  claim 2  wherein the sizes of the first transistor, the second transistor, the third transistor, and the fourth transistor are provided according to a sizing equation given by the following: 
       
         
           
             
               
                 I 
                 PA 
               
               = 
               
                 
                   I 
                   ref 
                 
                  
                 
                   
                     E 
                     PA 
                   
                   
                     E 
                     ref 
                   
                 
                  
                 
                   
                     
                       
                         E 
                         2 
                       
                        
                       
                         E 
                         3 
                       
                     
                     
                       
                         E 
                         1 
                       
                        
                       
                         E 
                         4 
                       
                     
                   
                 
               
             
           
         
       
       wherein the sizing equation relates a current of the amplifying transistor (I PA ) to a current of the reference transistor (I ref ), an emitter area of the reference transistor (E ref ), an emitter area of the amplifying transistor (E PA ), an emitter area of the first transistor (E 1 ), an emitter area of the second transistor (E 2 ), an emitter area of the third transistor (E 3 ), and an emitter area of the fourth transistor (E 4 ). 
     
     
         4 . The power density matching circuit of  claim 3  wherein a current density in the amplifying transistor relative to the reference transistor (J PA/ref ) is given by a square root of ((E 2 E 3 )/(E 1 E 4 )). 
     
     
         5 . The power density matching circuit of  claim 4  wherein J PA/ref =2 and E 4 =4E 1 =4E 2 =4E 3 . 
     
     
         6 . The power density matching circuit of  claim 1  wherein the power density matching circuit is configured to set a first power density associated with the reference transistor and to set a second power density associated with the amplifying transistor. 
     
     
         7 . The power density matching circuit of  claim 6  wherein the first power density is a function of a reference voltage level provided to the reference transistor. 
     
     
         8 . The power density matching circuit of  claim 7  wherein the second power density is a function of the supply voltage received at the supply node. 
     
     
         9 . The power density matching circuit of  claim 8  wherein the reference voltage level is less than the supply voltage. 
     
     
         10 . The power density matching circuit of  claim 1  further comprising an inductor coupled to the amplifying node. 
     
     
         11 . The power density matching circuit of  claim 1  wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor. 
     
     
         12 . A semiconductor die comprising:
 a packaging substrate configured to receive a plurality of components;   a plurality of connection pads formed on the packaging substrate; and   a power density matching circuit including a supply node configured to receive a supply voltage; a differential node configured to receive a signal from a differential amplifier; a reference node configured to provide a bias signal to a reference transistor; an amplifying node configured to provide a bias signal to an amplifying transistor; and a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.   
     
     
         13 . The semiconductor die of  claim 12  wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor. 
     
     
         14 . The semiconductor die of  claim 12  wherein temperature independent current translation provides power density matching between the amplifying transistor and the reference transistor. 
     
     
         15 . The semiconductor die of  claim 12  further comprising an inductor coupled to the amplifying node. 
     
     
         16 . The semiconductor die of  claim 12  wherein the power density matching circuit is configured to set a first power density associated with the reference transistor and to set a second power density associated with the amplifying transistor. 
     
     
         17 . A wireless device comprising:
 a transceiver configured to process radio-frequency signals;   an antenna in communication with the transceiver configured to facilitate transmission of an amplified radio-frequency signal; and   a power amplifier module connected to the transceiver and configured to generate the amplified radio-frequency signal, the power amplifier module including a supply node configured to receive a supply voltage; a differential node configured to receive a signal from a differential amplifier; a reference node configured to provide a bias signal to a reference transistor; an amplifying node configured to provide a bias signal to an amplifying transistor; and a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.   
     
     
         18 . The wireless device of  claim 17  wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor. 
     
     
         19 . The wireless device of  claim 17  wherein temperature independent current translation provides power density matching between the amplifying transistor and the reference transistor. 
     
     
         20 . The wireless device of  claim 17  wherein the power density matching circuit is configured to set a first power density associated with the reference transistor and to set a second power density associated with the amplifying transistor.