US2019355662A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: RENESAS ELECTRONICS CORPPriority: Jun 14, 2010Filed: Jul 30, 2019Published: Nov 21, 2019
Est. expiryJun 14, 2030(~3.9 yrs left)· nominal 20-yr term from priority
H10P 95/064H10P 74/238H10P 50/283H10P 14/6922H10P 14/662H10P 14/418H10D 64/0112H10W 20/063H10W 20/40H10W 20/0698H10W 20/435H10W 20/425H10W 20/083H10W 20/081H10W 20/077H10W 20/069H10W 20/066H10W 20/47H10W 20/039H10W 20/033H10W 20/20H01L 21/76895H01L 23/53295H01L 21/31111H01L 21/76805H01L 23/481H01L 29/7833H01L 21/76802H01L 23/53238H01L 23/485H01L 21/31055H01L 21/76897H01L 22/26H01L 23/535H01L 21/823475H01L 21/76885H01L 23/5283H01L 29/66477H01L 21/76843H01L 23/53266H01L 21/76852H01L 21/76889H01L 21/76834H01L 21/28518H01L 21/02126H01L 21/022H01L 21/28568H10D 84/0149H10D 84/038H10D 30/601H10D 30/021
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Claims

Abstract

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first interlayer insulating film formed on a semiconductor substrate;   a first plug formed inside the first interlayer insulating film;   a second interlayer insulating film formed on the first interlayer insulating film and having a dielectric constant lower than a dielectric constant of silicon oxide; and   a first buried wiring formed inside the second interlayer insulating film and connected to the first plug,   an upper surface of the first plug being formed at a position higher than an upper surface of the first interlayer insulating film, and   a lower surface of the first buried wiring being formed at a position lower than the upper surface of the first plug.

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