Inverse tone direct print euv lithography enabled by selective material deposition

Abstract

Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.

What is claimed is: 
     
         1 . A method for fabricating a pattern of vertical fins in a semiconductor structure, the method comprising:
 providing a semiconductor material stack including a plurality of layers; and   creating an inverse tone direct print pattern in the semiconductor material stack, where a critical dimension of the inverse tone direct print pattern is defined by selective sidewall atomic layer deposition on sidewalls of a mandrel pattern formed by vertical directional etching in the semiconductor material stack, to create trenches in at least one layer in the plurality of layers.   
     
     
         2 . The method of  claim 1 , wherein the selective sidewall atomic layer deposition creates sidewall spacers on sidewalls of the mandrel pattern on a fin hard mask stack. 
     
     
         3 . The method of  claim 1 , wherein the inverse tone direct print pattern in the semiconductor material stack is created by selective bottom-up gap fill in the trenches in the at least one layer in the plurality of layers. 
     
     
         4 . The method of  claim 1 , wherein the semiconductor material stack includes:
 a semiconductor substrate layer;   a fin hard mask stack, including one or more layers, disposed on the semiconductor substrate layer;   a first material layer, consisting of a first material, disposed on the fin hard mask stack; and   a photolithography stack, including one or more layers, disposed on the first material layer; and   wherein the method includes:
 forming an inverse tone direct print pattern on a top layer of the photolithography stack using direct print lithography; 
 performing a first vertical directional etching in the photolithography stack and in the first material layer to form a mandrel pattern in the first material layer; and 
 performing selective sidewall atomic layer deposition to create sidewall spacers on sidewalls of the mandrel pattern disposed on the fin hard mask stack. 
   
     
     
         5 . The method of  claim 4 , further comprising:
 performing trench fill with a second material to fill only trenches that were formed between the sidewall spacers on sidewalls of the mandrel pattern;   performing etching to remove the first material, the mandrel pattern, and the sidewall spacers, leaving the second material disposed, in a first pattern following a pattern of the trenches that were formed between the sidewall spacers, on the fin hard mask stack;   performing second vertical directional etching in the fin hard mask stack and in the semiconductor substrate layer only where layers are vertically exposed outside of the first pattern of the second material disposed on the fin hard mask stack, to form vertical fins in a vertical fin pattern in the semiconductor substrate layer; and   removing, after the second vertical directional etching, the second material and the fin hard mask stack, exposing the vertical fins in the vertical fin pattern formed in the semiconductor substrate layer.   
     
     
         6 . The method of  claim 5 , wherein the first material comprises silicon dioxide and the second material comprises transition metal oxides. 
     
     
         7 . The method of  claim 6 , wherein the transition metal is one of titanium, tantalum, or tungsten. 
     
     
         8 . The method of  claim 5 , wherein the sidewall spacers on the sidewalls of the mandrel pattern in the first material layer comprise silicon dioxide. 
     
     
         9 . The method of  claim 5 , wherein the fin hard mask stack comprises three layers including a silicon nitride layer disposed directly on a silicon dioxide layer, and which is disposed directly on a silicon nitride layer. 
     
     
         10 . The method of  claim 5 , wherein the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. 
     
     
         11 . The method of  claim 5 , wherein the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance. 
     
     
         12 . A semiconductor structure comprising:
 a plurality of vertical fins in a vertical fin pattern, wherein adjacent vertical fins in the vertical fin pattern are all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein pairs of adjacent vertical fins in the vertical fin pattern on a substrate, along the critical dimension, are separated by a constant pitch value at near zero tolerance. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein the constant pitch value is smaller than 76 nm. 
     
     
         15 . The semiconductor structure of  claim 13 , wherein the near zero tolerance is lower than 0.1 nm. 
     
     
         16 . The semiconductor structure of  claim 12 , wherein the plurality of vertical fins in a vertical fin pattern on a substrate on a semiconductor chip comprise at least one of:
 a plurality of vertical fin field-effect transistor (finFET) devices; or   a plurality of vertical transistor devices.   
     
     
         17 . The semiconductor structure of  claim 12 , wherein the plurality of vertical fins in a vertical fin pattern on a substrate on a semiconductor chip comprise a plurality of back-end-of-line vertical metallization structures. 
     
     
         18 . A method for fabricating a pattern of vertical fins in a semiconductor structure, the method comprising:
 providing a semiconductor material stack including a plurality of layers directly on a semiconductor substrate layer;   forming an inverse tone direct print pattern in the semiconductor material stack;   performing vertical directional etching according to the inverse tone direct print pattern to form vertical fins in a vertical fin pattern in the semiconductor substrate layer, wherein the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower.   
     
     
         19 . The method of  claim 18 , wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance. 
     
     
         20 . The method of  claim 19 , wherein the constant pitch value is smaller than 76 nm, and the near zero tolerance is lower than 0.1 nm.