Methods, apparatus, and system for a semiconductor device comprising gates with short heights

Abstract

At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

1 .- 7 . (Canceled) 
     
     
         8 . A semiconductor device, comprising:
 a semiconductor substrate;   an active area disposed on the semiconductor substrate;   a shallow trench isolation (STI) disposed in the silicon substrate adjacent to the active area;   a gate disposed over the active area and the STI;   a first spacer disposed on one gate sidewall and a second spacer disposed on another gate sidewall, wherein a top of the gate is below a top of the first spacer and a top of the second spacer; and   a silicon nitride cap disposed on the gate, on the top of the first spacer, and on the top of the second spacer.   
     
     
         9 . The semiconductor device of  claim 8 , further comprising:
 a source disposed over the active area and the STI and adjacent to a first side of the gate; and   a drain disposed over the active area and the STI and adjacent to a second side of the gate.   
     
     
         10 . The semiconductor device of  claim 9 , further comprising:
 a source contact disposed over the source over the active area;   a drain contact disposed over the drain over the active area; and   a gate contact disposed over the gate over the STI.   
     
     
         11 . The semiconductor device of  claim 10 , further comprising:
 a dielectric material disposed over the source over the STI and over the drain over the STI.   
     
     
         12 . The semiconductor device of  claim 8 , wherein the silicon nitride cap has a height of about 10 nm. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the gate has a height above the semiconductor substrate of less than about 80 nm. 
     
     
         14 . A system, comprising:
 a semiconductor device processing system to manufacture a semiconductor device; and   a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system;   wherein the semiconductor device processing system is adapted to:
 form a gate over at least one active area disposed on a semiconductor substrate; 
 form a first spacer disposed on one gate sidewall and a second spacer disposed on another gate sidewall; 
 form a dielectric material adjacent the first spacer and adjacent the second spacer; 
 recess the gate to below a top of the first spacer and a top of the second spacer; 
 form a silicon nitride liner on a top of the recessed gate; 
 grow a silicon nitride cap selectively on the silicon nitride liner and at least on a top of the first spacer and a top of the second spacer; and 
 form contacts to the gate and the active area, wherein contact formation is self-aligned by the silicon nitride cap. 
   
     
     
         15 . The system of  claim 14 , wherein the semiconductor device processing system is adapted to form the silicon nitride liner by:
 depositing by atomic layer deposition (ALD) silicon nitride on a top of the recessed gate, on an exposed sidewall portion and a top of the first spacer, on an exposed sidewall portion and a top of the second spacer, and on a top of the dielectric material;   coating the silicon nitride with a spin-on carbon polymer;   recessing the spin-on carbon polymer to below the top of the first spacer and the top of the second spacer, to yield recessed spin-on carbon polymer;   removing the silicon nitride above the recessed spin-on carbon polymer, to yield the silicon nitride liner; and   removing the recessed spin-on carbon polymer.   
     
     
         16 . The system of  claim 14 , wherein the semiconductor device processing system is adapted to grow the silicon nitride cap by treating the dielectric material to prevent silicon nitride growth on the dielectric material. 
     
     
         17 . The system of  claim 14 , wherein the semiconductor device processing system is adapted to further grow the silicon nitride cap over a portion of the dielectric material. 
     
     
         18 . The system of  claim 14 , wherein the semiconductor device processing system is adapted to extend the dielectric material to the same height as the silicon nitride cap. 
     
     
         19 . The system of  claim 14 , wherein the semiconductor device processing system is adapted to form the contact to the gate at a position disposed laterally away from the active area. 
     
     
         20 . The system of  claim 14 , wherein the semiconductor device processing system is adapted to form silicon oxide as the dielectric material. 
     
     
         21 . A semiconductor device, comprising:
 a semiconductor substrate;   an active area disposed on the semiconductor substrate;   a shallow trench isolation (STI) disposed in the silicon substrate adjacent to the active area;   a gate disposed over the active area and the STI;   a first spacer disposed on one gate sidewall and a second spacer disposed on another gate sidewall, wherein a top of the gate is below a top of the first spacer and a top of the second spacer;   a source disposed over the active area and the STI and adjacent to a first side of the gate; and   a drain disposed over the active area and the STI and adjacent to a second side of the gate;   a dielectric material disposed over the source over the STI and over the drain over the STI; and   a silicon nitride cap disposed on the gate, on the top of the first spacer, on the top of the second spacer, on a portion of a top of dielectric material disposed over the source, and on a portion of a top of dielectric material disposed over the drain.   
     
     
         22 . The semiconductor device of  claim 21 , further comprising:
 a source contact disposed over the source over the active area;   a drain contact disposed over the drain over the active area; and   a gate contact disposed over the gate over the STI.   
     
     
         23 . The semiconductor device of  claim 21 , wherein the silicon nitride cap has a height of about 10 nm. 
     
     
         24 . The semiconductor device of  claim 21 , wherein the gate has a height above the semiconductor substrate of less than about 80 nm.