Control method for memory device

Abstract

According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.

What is claimed is: 
     
         1 . A method of operating a memory device that comprises a plurality of electrodes, the method comprising:
 supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode;   stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode; and   supplying a first potential to the first electrode after stopping supply of the third potential.   
     
     
         2 . The method of operating a memory device according to  claim 1 , further comprising:
 reducing the potential of the second electrode by allowing the second potential to decay to a value less than the first value; and   supplying the second potential to the second electrode at a second level less than the first value but greater than the value to which the second electrode decayed.   
     
     
         3 . The method of operating a memory device according to  claim 2 , further comprising supplying the second potential to the second electrode at the second level simultaneously with the supplying of the first potential to the first electrode. 
     
     
         4 . The method of operating a memory device according to  claim 2 , further comprising:
 supplying the second potential to the second electrode at the second level before supplying of the first potential to the first electrode.   
     
     
         5 . The method of operating a memory device according to  claim 1 , further comprising:
 supplying a fourth potential to a fourth electrode before supplying any of the first, second, and third potentials to the first, second, and third electrodes, respectively.   
     
     
         6 . The method of operating a memory device according to  claim 5 , further comprising:
 supplying a fifth potential at a first level to a fifth electrode while applying the first potential to the first electrode; and   increasing the fifth potential from the first level thereof to a second level that is greater than the first level.   
     
     
         7 . The method of operating a memory device of  claim 6 , wherein
 the memory device includes a three-dimensional memory array,   the first electrode is a first word line of the memory array other than a word line connected to a memory cell to be written to, and   the fifth electrode is a second word line of the memory array connected to a memory cell to be written to.   
     
     
         8 . The method of operating a memory device of  claim 7 , wherein
 the memory array further includes a seventh electrode,   the first electrode is located between the seventh electrode and the second electrode, and   the method further comprises:
 supplying a seventh potential to the seventh electrode before supplying the second and third potentials to the second and third electrodes, respectively. 
   
     
     
         9 . The method of operating a memory device according to  claim 1 , further comprising:
 supplying a fourth potential to a fourth electrode simultaneously with the supplying of the second and third potentials to the second and third electrodes, respectively.   
     
     
         10 . The method of operating a memory device according to  claim 9 , wherein
 the second and third electrodes are selection gates, and   a sixth electrode is located over the second and third electrodes, and   the method further comprises:
 supplying a sixth potential to the sixth electrode before supplying the second and third potentials to the second and third electrodes, respectively. 
   
     
     
         11 . A method of writing data into memory cells of a three-dimensional memory array having a plurality of first selection gates located one upon another, a plurality of word lines, located over the first selection gates and stacked one upon another, a plurality of second selection gates located over the word lines and located one upon another, and a plurality of columnar bodies, having a conductive core, extending through the first and second selection gates and the word lines, wherein memory cells are formed between conductive core of the columnar bodies and the words lines penetrated by the columns, the method comprising:
 applying a second potential of a first value to a first one of the second selection gates;   applying a third potential to a second one of the second selection gates while the second potential of the first value is applied to the first one of the second selection gates;   stopping application of the third potential to the second one of the second selection gates whereby the potential of the second one of the second selection gates decays;   reducing the second potential applied to the first one of the second selection gates while the potential of the second one of the second selection gates decays; and   applying a first potential to a first word line which is connected to a memory cell to be written to when the potential of the first one of the selection gates is less than the first level.   
     
     
         12 . The method according to  claim 11 , further comprising:
 reducing the second potential applied to the first one of the second selection gates while the potential of the second one of the second selection gates decays by stopping the application of the second potential at the first level to the first one of the second selection gates.   
     
     
         13 . The method according to  claim 11 , further comprising:
 applying the second potential to the first one of the second selection gates at a second value less than the first value after stopping application of the third potential to the second one of the second selection gates to allow the potential of the second one of the second selection gates decay.   
     
     
         14 . The method according to  claim 12 , further comprising:
 applying the second potential to the first one of the second selection gates at a second value less than the first value after stopping the application of the second potential at the first level to the first one of the second selection gates.   
     
     
         15 . The method according to  claim 14 , further comprising:
 applying the first potential to the first word line simultaneously with the applying of the second potential to the first one of the second selection gates at a second value less than the first value.   
     
     
         16 . The method according to  claim 11 , further comprising:
 applying a fourth potential to a second word line, not connected to the memory cell to be written to, before applying the second and third potentials to the first and second ones of the second selection gates, respectively, wherein   the second word line is located between the first word line and the second plurality of selection gates.   
     
     
         17 . The method according to claim.  11 , further comprising:
 applying a fourth potential to a second word line, not connected to the memory cell to be written to, simultaneously with the application of the second and third potentials to the first and second ones of the second selection gates, respectively, wherein   the second word line is located between the first word line and the second plurality of selection gates.   
     
     
         18 . The method according to  claim 11 , further comprising:
 applying the first potential to the first word line at a first value initially, and thereafter applying the first potential to the first word line at a second value greater than the first value.   
     
     
         19 . The method according to  claim 11 , further comprising:
 applying a fifth potential to a third one of the second selection gates before applying the second and third potentials to the first and second ones of the second selection gates; wherein   the first and second ones of the second selection gates are located between the third one of the selection gates and the word lines.   
     
     
         20 . The method according to  claim 11 , wherein at least one of the first plurality of selection gates is maintained at a voltage of 0.