Implied directory state updates

Abstract

A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to receipt of the request, to reflect the new state. A copy of the particular line is sent in response to the request

1 - 21 . (canceled) 
     
     
         22 . An apparatus comprising:
 graphics processing circuitry to perform graphics operations;   a coherent interconnect fabric comprising:
 packet communication links to carry data packets, 
 packet switching circuitry to establish virtual channels over the packet communication links and to route the data packets in accordance with the virtual channels, and 
 coherence circuitry to manage coherency states associated with data transmitted in the data packets; 
   a graphics interconnect to couple the graphics processing circuitry to the coherent interconnect fabric;   a memory controller to couple the graphics processing circuitry to a first type of system memory device and a second type of system memory device, wherein first type of system memory device is associated with a first level of performance and the second type of system memory device is associated with a second level of performance greater than the first level of performance, wherein the memory controller is to use the second type of system memory device as a cache to the first type of system memory device;   input/output (I/O) interconnect circuitry to couple the coherent interconnect fabric to one or more I/O interfaces of one or more I/O devices and/or one or more I/O interconnects; and   power management circuitry to independently regulate power to each of a plurality of domains, including a graphics domain associated with the graphics processing circuitry.   
     
     
         23 . The apparatus of  claim 22 , further comprising:
 a distributed directory to store the coherency states, the coherence circuitry to update the coherency states in the distributed directory based, at least in part, on snoop messages transmitted over the packet communication links.   
     
     
         24 . The apparatus of  claim 22 , wherein the packet processing circuitry is to implement credit-based flow control to route the data packets through the virtual channels. 
     
     
         25 . The apparatus of  claim 22 , wherein the coherency states include an exclusive state, a modified state, a clean state, an invalid state, and a forward state. 
     
     
         26 . The apparatus of  claim 22 , wherein different data packets are associated with different traffic classes, the packet processing circuitry to process the data packets in accordance with the associated traffic classes. 
     
     
         27 . The apparatus of  claim 22 , wherein different data packets are associated with different priority values, the packet processing circuitry to process the data packets in accordance with the different priorities. 
     
     
         28 . The apparatus of  claim 22 , wherein the plurality of cores and coherent interconnect fabric are integrated on a first processor chip, the coherent interconnect fabric further comprising:
 off-chip coherent interconnect circuitry to extend the coherent interconnect fabric to a second coherent interconnect fabric on a second processor chip.   
     
     
         29 . The apparatus of  claim 28 , wherein the off-chip coherent interconnect circuitry is a first off-chip coherent interconnect circuitry, the coherent interconnect fabric further comprising:
 a second off-chip coherent interconnect circuitry to extend the coherent interconnect fabric to a third coherent interconnect fabric on a third processor chip.   
     
     
         30 . The apparatus of  claim 29 , wherein the first off-chip coherent interconnect circuitry is coupled to a first off-chip link coupled to the second coherent interconnect fabric on the second processor chip, and the second off-chip coherent interconnect circuitry is coupled to a second off-chip link coupled to the third coherent interconnect fabric on the third processor chip. 
     
     
         31 . The apparatus of  claim 22 , wherein the one or more I/O interconnects comprise at least one PCI Express interconnect. 
     
     
         32 . The apparatus of  claim 22 , wherein the packet communication links comprise a width of N bits transmitted over N data lines and the coherent interconnect fabric further comprises data link circuitry to process data flits comprising M bits of data where M>N. 
     
     
         33 . The apparatus of  claim 32 , wherein the M bits of data from a flit is to be mapped to successive N-bit sets of data transmitted over the N data lines. 
     
     
         34 . The apparatus of  claim 22 , wherein the packet processing circuitry comprises at least one buffer to temporarily store the data packets carried over the packet communication links.