US2019348542A1PendingUtilityA1
Semiconductor device and method of manufacturing the semiconductor device
Est. expirySep 29, 2036(~10.2 yrs left)· nominal 20-yr term from priority
Inventors:Tomohiro Yamashita
H10D 64/0112H01L 29/665H01L 29/785H01L 29/7851H01L 29/0653H01L 21/28518H01L 29/0847H01L 29/792H01L 29/66833H01L 29/45H01L 29/40117H01L 29/66795H01L 29/42344H01L 27/11568H10D 30/6215H10D 30/611H10D 30/024H10D 30/68H10D 64/62H10D 64/037H10D 62/151H10D 62/116H10D 30/6211H10D 30/696H10D 30/0413H10D 30/0212H10D 30/62H10D 64/512H10D 64/01H10D 62/117H10D 30/69H10B 43/30
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Claims
Abstract
Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.
Claims
exact text as granted — not AI-modified1 - 12 . (canceled)
13 . A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) providing a semiconductor substrate; (b) retracting a part of a top of the semiconductor substrate, thereby forming a plurality of protrusions that are each a portion of the semiconductor substrate, protrude from the part of the top of the semiconductor substrate, and extend in a first direction along the top of the semiconductor substrate; (c) forming an element isolation film that fills a first trench between the protrusions adjacent to each other; (d) forming a first gate electrode that covers tops and side faces of the protrusions with a first insulating film in between over the element isolation film; (e) after the step (d), forming a second insulating film as a charge storage part, a first semiconductor film, and a first metal film in order over the semiconductor substrate, thereby filling a space between the protrusions arranged in a second direction orthogonal to the first direction with a stacked film including the first semiconductor film and the first metal film; (f) processing the stacked film to form a second gate electrode including the stacked film that is adjacent to one side face of the first gate electrode with the second insulating film in between, and covers the tops and the side faces of the protrusions with the second insulating film in between; and (g) forming source and drain regions in a surface of each of the protrusions beside a pattern including the first gate electrode and the second gate electrode.
14 . The method according to claim 13 ,
wherein in the step (e), the second insulating film, the first semiconductor film, the first metal film, and a second semiconductor film are formed in order over the semiconductor substrate, thereby the space between the protrusions arranged in the second direction is filled with a stacked film including the first semiconductor film, the first metal film, and the second semiconductor film; the method further comprising the step of: (h) after the step (g), siliciding a top of the second semiconductor film.
15 . The method according to claim 13 ,
wherein in the step (e), the second insulating film, the first semiconductor film, the first metal film, and a second semiconductor film are formed in order over the semiconductor substrate, thereby the space between the protrusions arranged in the second direction is filled with the stacked film including the first semiconductor film, the first metal film, and the second semiconductor film, the method further comprising the steps of: (h) after the step (g), removing the second semiconductor film to form a second trench over the second insulating film; and (i) after the step (h), filling the second trench with a second metal film.Join the waitlist — get patent alerts
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