Silicon carbide semiconductor device, power converter, and method of manufacturing silicon carbide semiconductor device

Abstract

A drift layer has a first conductivity type and is provided on a silicon carbide substrate. A well region has a second conductivity type and is provided on the drift layer. A source region has the first conductivity type and is provided on the well region. A gate trench has an inner surface with a bottom located at a deeper position than the well region and a lateral part continuous with the bottom. An electric field relaxation region has the second conductivity type and has at least a part located below the bottom of the gate trench. A surge relaxation region has the first conductivity type, contacts at least a part of the bottom of the gate trench, and is separated from the drift layer by the electric field relaxation region.

What is claimed is: 
     
         1 . A silicon carbide semiconductor device comprising:
 a silicon carbide substrate; and   a semiconductor layer provided on the silicon carbide substrate,   the semiconductor layer including:   a drift layer having a first conductivity type and being provided on the silicon carbide substrate;   a well region having a second conductivity type different from the first conductivity type and being provided on the drift layer,   a source region having the first conductivity type and being provided on the well region;   a gate trench having an inner surface with a bottom located at a deeper position than the well region and a lateral part continuous with the bottom;   an electric field relaxation region having the second conductivity type and having at least a part located below the bottom of the gate trench; and   a surge relaxation region having the first conductivity type, contacting at least a part of the bottom of the gate trench, and being separated from the drift layer by the electric field relaxation region.   
     
     
         2 . The silicon carbide semiconductor device according to  claim 1 , wherein
 the first conductivity type is an n-type and the second conductivity type is a p-type.   
     
     
         3 . The silicon carbide semiconductor device according to  claim 1 , further comprising a source electrode connected to the source region, wherein
 the semiconductor layer includes a source trench reaching the surge relaxation region, and the source electrode passes through the source trench to contact the surge relaxation region.   
     
     
         4 . The silicon carbide semiconductor device according to  claim 3 , wherein
 the source trench reaches the electric field relaxation region, and the source electrode passes through the source trench to contact the electric field relaxation region.   
     
     
         5 . The silicon carbide semiconductor device according to  claim 1 , wherein
 the semiconductor layer includes a first connection region having the first conductivity type, extending along the inner surface of the gate trench, and connecting the surge relaxation region to the source region.   
     
     
         6 . The silicon carbide semiconductor device according to  claim 5 , wherein
 the semiconductor layer includes a second connection region having the second conductivity type and connecting the electric field relaxation region to the well region, and   the first connection region is separated from the drift layer by the second connection region.   
     
     
         7 . The silicon carbide semiconductor device according to  claim 1 , wherein
 the electric field relaxation region includes a contact part contacting the gate trench and a separated part separated from the gate trench by the contact part, and the contact part has a lower impurity concentration than the separated part.   
     
     
         8 . A power converter comprising:
 a main converter circuit including the silicon carbide semiconductor device according to  claim 1 , and converting input power to converted power and outputting the converted power;   a driver circuit that outputs a driving signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and   a control circuit that outputs a control signal for controlling the driver circuit to the driver circuit.   
     
     
         9 . A method of manufacturing a silicon carbide semiconductor device comprising:
 preparing a silicon carbide substrate and a semiconductor layer being provided on the silicon carbide substrate and including a drift layer having a first conductivity type;   forming a preliminary trench by etching the drift layer;   forming an electric field relaxation region by implanting impurities of a second conductivity type different from the first conductivity type into a bottom of the preliminary trench;   forming a gate trench having a greater depth than the preliminary trench by etching the bottom of the preliminary trench; and   forming a surge relaxation region contacting at least a part of a bottom of the gate trench and being separated from the drift layer by the electric field relaxation region by implanting impurities of the first conductivity type into the bottom of the gate trench.   
     
     
         10 . A method of manufacturing a silicon carbide semiconductor device comprising a silicon carbide substrate and a semiconductor layer provided on the silicon carbide substrate, the semiconductor layer including a drift layer, a well region, a source region, a gate trench, an electric field relaxation region, a surge relaxation region, a first connection region, and a second connection region, the drift layer having a first conductivity type and being provided on the silicon carbide substrate, the well region having a second conductivity type different from the first conductivity type and being provided on the drift layer, the source region having the first conductivity type and being provided on the well region, the gate trench having an inner surface with a bottom located at a deeper position than the well region and a lateral part continuous with the bottom, the electric field relaxation region having the second conductivity type and having at least a part located below the bottom of the gate trench, the surge relaxation region having the first conductivity type, contacting at least a part of the bottom of the gate trench, and being separated from the drift layer by the electric field relaxation region, the first connection region having the first conductivity type, extending along the inner surface of the gate trench, and connecting the surge relaxation region to the source region, the second connection region having the second conductivity type and connecting the electric field relaxation region to the well region, the first connection region being separated from the drift layer by the second connection region, the method comprising:
 forming the gate trench by etching the semiconductor layer;   forming the first connection region by adding impurities of the first conductivity type by oblique ion implantation into the lateral part of the gate trench; and   forming the second connection region by adding impurities of the second conductivity type by rotating ion implantation into the lateral part of the gate trench.