Nonvolatile memory apparatus and verification write method thereof for reducing program time

Abstract

A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

What is claimed is: 
     
         1 . A write operation method of a non-volatile memory apparatus, the method comprising:
 clamping a current flowing through a memory cell to maintain a range of the current flowing through the memory cell below a program current;   applying a verification-write voltage to the memory cell, wherein the verification-write voltage has a voltage level at which a snap-back of the memory cell in a reset state does not occur and higher level than a read voltage; and   increasing the amount of the program current based on whether a snap-back of the memory cell occurs.   
     
     
         2 . The write operation method of  claim 1 , further comprising ending the write operation when the snap-back does not occur. 
     
     
         3 . The write operation method of  claim 1 , further comprising programming the memory cell with the program current having the increased amount when the snap-back occurs. 
     
     
         4 . The write operation method of  claim 1 , further performing repeatedly clamping the current flowing through the memory cell, applying the verification-write operation, and increasing the amount of the program current until the snap-back does not occur. 
     
     
         5 . The write operation method of  claim 1 , wherein increasing the amount of the program current is performed gradually based on a number of iterations of performing the write operations. 
     
     
         6 . The write operation method of  claim 1 , further comprising counting a number of iterations of performing the write operations, wherein, if the number of iterations of performing the write operations reaches a maximum, the write operation is ended. 
     
     
         7 . A non-volatile memory apparatus comprising:
 a voltage generation circuit coupled to a memory cell and configured to provide a verification-write voltage to the memory cell, wherein the verification-write voltage has a voltage level at which a snap-back of the memory cell in a set state only occurs, and has a higher level than a read voltage;   a program current generation circuit configured to increase a program current based on whether the snap-back of the memory cell occurs; and   a clamping circuit coupled to the voltage generation circuit and configured to clamp the memory cell current to maintain a range of a memory cell current below the program current.   
     
     
         8 . The non-volatile memory apparatus of  claim 7 , further comprising a sense amplifier configured to generate a detection signal by detecting the memory cell current, wherein the program current generation circuit includes:
 a program controller configured to generate a current update signal and a program end signal based on the detection signal; and   a clamping controller configured to generate a clamping control signal by increasing the program current according to the current update signal.   
     
     
         9 . The non-volatile memory apparatus of  claim 8 , wherein the sense amplifier generates the detection signal having a first level when the snap-back of the memory cell current occurs, and generates the detection signal having a second level when the snap-back of the memory cell current is less than the threshold current value. 
     
     
         10 . The non-volatile memory apparatus of  claim 8 , wherein the program controller increases a value of the current update signal every time the program controller receives the detection signal having the first level. 
     
     
         11 . The non-volatile memory apparatus of  claim 10 , wherein the program controller counts a number of the detection signal having the first level, and generates the program end signal when the number of the detection signal reaches a maximum. 
     
     
         12 . The non-volatile memory apparatus of  claim 10 , wherein the program controller generates the program end signal when the value of the current update signal reaches a maximum. 
     
     
         13 . The non-volatile memory apparatus of  claim 10 , wherein the program controller generates the program end signal in response to the detection signal having the second level. 
     
     
         14 . The non-volatile memory apparatus of  claim 8 , wherein the clamping controller includes:
 a variable current source configured to increase the program current based on the current update signal; and   a clamping control signal generator configured to generate the clamping control signal having a voltage level corresponding to an amount of the program current.   
     
     
         15 . The non-volatile memory apparatus of  claim 8 , wherein the clamping circuit applies a clamping current substantially the same as the program current to the voltage generation circuit in response to the clamping control signal.