US2019342994A1PendingUtilityA1

Selective dielectric resin application on circuitized core layers

Assignee: IBMPriority: Dec 18, 2017Filed: Jul 15, 2019Published: Nov 7, 2019
Est. expiryDec 18, 2037(~11.4 yrs left)· nominal 20-yr term from priority
H05K 1/09H05K 3/429H05K 3/4664H05K 1/11H05K 3/0014H05K 2203/1453H05K 1/0284H05K 3/4602H05K 2203/0278H05K 1/0373H05K 1/14H05K 3/4611H05K 2201/0187H05K 1/0366H05K 1/115
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Claims

Abstract

A process of manufacturing a multiple-layer printed circuit board includes selectively applying a dielectric resin to a region of a circuitized core layer. The process also includes partially curing the dielectric resin prior to performing a lamination cycle to form the multiple-layer printed circuit board that includes the circuitized core layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A circuitized core layer for multiple-layer printed circuit board manufacturing, the circuitized core layer comprising a partially cured dielectric resin disposed within a region associated with increased resin demand. 
     
     
         2 . The circuitized core layer of  claim 1 , wherein the partially cured dielectric resin is formed by:
 utilizing an inkjet printer to dispense a dielectric resin within the region; and   partially curing the dielectric resin.   
     
     
         3 . The circuitized core layer of  claim 1 , wherein the region associated with increased resin demand corresponds to an area between adjacent copper traces. 
     
     
         4 . The circuitized core layer of  claim 1 , wherein the region associated with increased resin demand is adjacent to a location of a plated through hole (PTH) to be formed after performing a lamination cycle to form a multiple-layer printed circuit board that includes the circuitized core layer. 
     
     
         5 . The circuitized core layer of  claim 1 , wherein the partially cured dielectric resin is substantially similar to a partially cured resin within a layer of pre-impregnated (prepreg) material adjacent to the region of the circuitized core layer in a layup that is laminated to form a multiple-layer printed circuit board that includes the circuitized core layer.

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