Semiconductor device and manufacturing method of semiconductor device

Abstract

A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a support substrate;   a semiconductor layer formed on the support substrate, the semiconductor layer comprising:
 a source region having a first conductivity type; 
 a drain region having the first conductivity type and formed separately from the source region; 
 a first semiconductor region of the first conductivity type surrounding the drain region; 
 a second semiconductor region having a second conductivity type opposite to the first conductivity type and surrounding the source region; 
 a third semiconductor region having the second conductivity type and overlapping with the first semiconductor region and the second semiconductor region in plan view; and 
 a fourth semiconductor region having the second conductivity type and formed between the third semiconductor region and the second semiconductor region, wherein no other semiconductor region having the first conductivity type is formed between the fourth semiconductor region and the third semiconductor region, 
   a first insulating region formed in the semiconductor layer between the source region and the drain region in plan view;   a gate insulating film formed on the semiconductor layer between the first insulating region and the source region; and   a gate electrode formed on the gate insulating film and the first insulating region.   
     
     
         22 . The semiconductor device according to  claim 21 , comprising:
 a second insulating region surrounding the gate electrode in plan view such that the second insulating film reaches the support substrate,   wherein a side surface of the second insulating region contacts the third semiconductor region and the second semiconductor region.   
     
     
         23 . The semiconductor device according to  claim 22 , wherein an impurity concentration of the second semiconductor region is greater than an impurity concentration of the fourth semiconductor region, and
 the impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the third semiconductor region.   
     
     
         24 . The semiconductor device according to  claim 21 , wherein an impurity concentration of the second semiconductor region is greater than an impurity concentration of the fourth semiconductor region, and
 the impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the third semiconductor region.   
     
     
         25 . The semiconductor device according to  claim 22 , wherein the fourth semiconductor region has:
 a first end portion in a side closer to the second semiconductor region; and   a second end portion in a side closer to the first semiconductor region, and   
       wherein the second end portion overlaps with the first insulating region in plan view. 
     
     
         26 . The semiconductor device according to  claim 25 , wherein the first end portion contacts the second insulating region. 
     
     
         27 . The semiconductor device according to  claim 21 , wherein the fourth semiconductor region is set apart from the third semiconductor region by a fifth semiconductor region, which has the second conductivity type and is formed between the third and fourth semiconductor regions. 
     
     
         28 . The semiconductor device according to  claim 21 , wherein the first conductivity type is n type, and the second conductivity type is p type. 
     
     
         29 . The semiconductor device according to  claim 21 , comprising a sixth semiconductor region of the first conductivity type below the third semiconductor region. 
     
     
         30 . The semiconductor device according to  claim 29 , wherein the sixth semiconductor region overlaps with the first semiconductor region and the second semiconductor region. 
     
     
         31 . The semiconductor device according to  claim 29 , wherein the sixth semiconductor region overlaps with the third semiconductor region. 
     
     
         32 . The semiconductor device according to  claim 22 , comprising:
 an interlayer insulating film formed over the semiconductor layer such that the interlayer insulating film covers the gate electrode,   wherein the side surface of the second insulating region contacts the interlayer insulating film.