Finfet-cascode laterally-diffused semiconductor device

Abstract

A semiconductor device includes a substrate consisting a first well region and a second well region including a first dopant and a second dopant, respectively. The second well region is located laterally from the first well region along a channel axis. One or more semiconductor fin structures having a channel region through the first well region are formed on the substrate. A drain region and a source region are formed on the semiconductor fin structures. The first well region and the drain region are formed to operate at a first operating voltage, and the second well region and the source region are formed to operate at a second operating voltage that is smaller than the first operating voltage. A first STI region is formed in the first well region and is used to extend a length of the channel region through the first well region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate having a first well region comprising a first dopant and a second well region comprising a second dopant;   one or more semiconductor fin structures formed on the substrate, the one or more semiconductor fin structures having a channel region along a channel axis through the first well region;   a drain region formed on the one or more semiconductor fin structures;   a source region formed on the one or more semiconductor fin structures, the first well region and the drain region being formed to operate at a first operating voltage, the second well region and the source region being formed to operate at a second operating voltage that is smaller than the first operating voltage;   a gate structure disposed on at least a portion of the one or more semiconductor fin structures; and   a first shallow-trench isolation (STI) region formed in the first well region and configured to extend a length of the channel region through the first well region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first STI region enables creation of a longer depletion region in the first well region by allowing formation of a depletion region around side walls and a bottom of the first STI region. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a second STI region formed adjacent to and/or in contact with the first well region configured to provide isolation and protection for the semiconductor device. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the first STI region and the second STI region are formed by using a dielectric material including silicon dioxide (SiO 2 ). 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a plurality of epitaxial growth structures formed on the one or more semiconductor fin structures, the plurality of epitaxial growth structures comprising a doping material having a doping concentration that is greater than that of at least one of the first dopant or the second dopant. 
     
     
         6 . The semiconductor device of  claim 5 , further comprising a dummy gate disposed on at least a portion of the one or more semiconductor fin structures, wherein the dummy gate is disposed between the gate structure and the drain region and between and in contact with two epitaxial growth structures of the plurality of epitaxial growth structures, wherein the dummy gate has a resistance that is directly proportional to a length of the dummy gate along the channel axis. 
     
     
         7 . The semiconductor device of  claim 6 , wherein a first epitaxial growth structure of the plurality of epitaxial growth structures is formed in between and in contact with the gate structure and the dummy gate, and wherein a second epitaxial growth structure of the plurality of epitaxial growth structures is formed in between and in contact with the dummy gate and the drain region. 
     
     
         8 . The semiconductor device of  claim 7 , further comprising a spacer disposed on the one or more semiconductor fin structures, wherein the spacer is disposed in between and in contact with the second epitaxial growth structure and the drain region. 
     
     
         9 . The semiconductor device of  claim 7 , wherein at least a portion of the one or more semiconductor fin structures located directly beneath the dummy gate comprises a doping material having a doping concentration that is smaller than that of at least one of the first dopant or the second dopant. 
     
     
         10 . The semiconductor device of  claim 9 , wherein at least a portion of the one or more semiconductor fin structures located directly beneath the gate structure or the drain region has a doping concentration that is smaller than that of the at least a portion of the one or more semiconductor fin structures located directly beneath the dummy gate with the doping material. 
     
     
         11 . A semiconductor device, comprising:
 a substrate;   a first well region in the substrate, the first well region comprising a first dopant;   a second well region in the substrate, the second well region comprising a second dopant, the second well region located laterally from the first well region along a channel axis;   one or more semiconductor fin structures formed on the substrate, the one or more semiconductor fin structures having a channel region through the first well region;   a drain region formed on the one or more semiconductor fin structures;   a source region formed on the one or more semiconductor fin structures, the first well region and the drain region being formed to operate at a first operating voltage, the second well region and the source region being formed to operate at a second operating voltage that is smaller than the first operating voltage;   a gate structure disposed on at least a portion of the one or more semiconductor fin structures; and   a first STI region formed in the first well region and configured to extend a length of the channel region through the first well region.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising a second STI region formed adjacent to and/or in contact with the first well region configured to provide isolation and protection for the semiconductor device, and wherein the first STI region and the second STI regions are formed of silicon dioxide (SiO 2 ). 
     
     
         13 . The semiconductor device of  claim 12 , further comprising a plurality of epitaxial growth structures formed on the one or more semiconductor fin structures, the plurality of epitaxial growth structures comprising a doping material having a doping concentration that is greater than that of at least one of the first dopant or the second dopant. 
     
     
         14 . The semiconductor device of  claim 13 , further comprising a dummy gate disposed on at least a portion of the one or more semiconductor fin structures, wherein the dummy gate is disposed between the gate structure and the drain region and between and in contact with two epitaxial growth structures of the plurality of epitaxial growth structures, wherein the dummy gate has a resistance that is directly proportional to a length of the dummy gate along the channel axis. 
     
     
         15 . The semiconductor device of  claim 14 , wherein a first epitaxial growth structure of the plurality of epitaxial growth structures is formed in between and in contact with the gate structure and the dummy gate, and wherein a second epitaxial growth structure of the plurality of epitaxial growth structures is formed in between and in contact with the dummy gate and the drain region. 
     
     
         16 . The semiconductor device of  claim 15 , further comprising a spacer disposed on the one or more semiconductor fin structures, wherein the spacer is disposed in between and in contact with the second epitaxial growth structure and the drain region. 
     
     
         17 . The semiconductor device of  claim 15 , wherein at least a portion of the one or more semiconductor fin structures located directly beneath the dummy gate comprises a doping material having a doping concentration that is smaller than that of at least one of the first dopant or the second dopant. 
     
     
         18 . The semiconductor device of  claim 17 , wherein at least a portion of the one or more semiconductor fin structures located directly beneath the gate structure or the drain region has a doping concentration that is smaller than that of the at least a portion of the one or more semiconductor fin structures located directly beneath the dummy gate with the doping material. 
     
     
         19 . A finFET-cascode laterally-diffused semiconductor device, the semiconductor device comprising:
 a first well region and a second well region including a first dopant and a second dopant, respectively, the first well region being formed in a substrate and the second well region formed laterally from the first well region along a channel axis;   one or more semiconductor fin structures having a channel region through the first well region;   a drain region and a source region formed on the one or more semiconductor fin structures;   the first well region and the drain region being formed to operate at a first operating voltage, the second well region and the source region being formed to operate at a second operating voltage that is smaller than the first operating voltage;   a first STI region formed in the first well region and configured to extend a length of the channel region through the first well region; and   a gate structure disposed on at least a portion of the one or more semiconductor fin structures.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising a second STI region formed adjacent to and/or in contact with the first well region configured to provide isolation and protection for the semiconductor device, and wherein the first STI region and the second STI regions are formed of silicon dioxide (SiO 2 ).