Semiconductor device and method for fabricating the same

Abstract

A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

What is claimed is: 
     
         1 . A method for fabricating semiconductor device, comprising:
 forming a first trench and a second trench in a substrate;   forming a shallow trench isolation (STI) in the first trench, wherein the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench; and   forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a liner in the first trench;   forming a dielectric layer on the liner in the first trench; and   performing an etching process to remove part of the dielectric layer and part of liner to form the STI.   
     
     
         3 . The method of  claim 2 , wherein the remaining dielectric layer forms the top portion of the STI and the remaining liner forms the bottom portion of the STI after performing the etching process. 
     
     
         4 . The method of  claim 2 , wherein an etchant of the etching process is selected from the group consisting of CH 3 F and O 2 . 
     
     
         5 . The method of  claim 2 , wherein the liner comprises silicon oxide and the dielectric layer comprises silicon nitride. 
     
     
         6 . The method of  claim 5 , wherein an etching selectivity of silicon oxide to silicon nitride is 20:1. 
     
     
         7 . The method of  claim 1 , wherein the top surfaces of the first gate structure and the second gate structure are coplanar. 
     
     
         8 . The method of  claim 1 , further comprising forming a hard mask on each of the first gate structure and the second gate structure after forming the conductive layer. 
     
     
         9 . The method of  claim 8 , wherein the top surfaces of the hard mask and the substrate are coplanar. 
     
     
         10 . The method of  claim 8 , wherein the hard mask comprises silicon nitride. 
     
     
         11 . A semiconductor device, comprising:
 a shallow trench isolation (STI) in a substrate, wherein the STI comprises:
 a bottom portion; and 
 a top portion on the bottom portion, wherein a top surface of the top portion is even with or higher than a top surface of the substrate and a top surface of the bottom portion adjacent to two sides of the top portion is lower than the top surface of the top portion. 
   
     
     
         12 . The semiconductor device of  claim 11 , wherein the top portion and the bottom portion comprise different material. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the top portion comprises silicon nitride and the bottom portion comprises silicon oxide. 
     
     
         14 . The semiconductor device of  claim 11 , wherein a bottom surface of the top portion is lower than the top surface of the bottom portion.