Memory system and operating method thereof

Abstract

There are provided a memory system and an operating method thereof. The memory system includes: a memory device for storing data in a program operation, and reading stored data and temporarily store the read data in a read operation; and a controller for transmitting data to the memory device, wherein the controller includes: a flash direct memory access (DMA) for reading and outputting the data temporarily stored in the memory device in the read operation; a buffer memory for storing the data output from the flash DMA; and a host DMA for reading the data stored in the buffer memory and outputting the read data to a host, wherein a first operation of storing the data temporarily stored in the memory device in the buffer memory and a second operation of outputting the data stored in the buffer memory to the host are performed in parallel.

What is claimed is: 
     
         1 . A memory system comprising:
 a memory device configured to store data in a program operation, and read stored data and temporarily store the read data in a read operation; and   a controller configured to transmit data to the memory device,   wherein the controller includes:   a flash direct memory access (DMA) configured to read and output the data temporarily stored in the memory device in the read operation;   a buffer memory configured to store the data output from the flash DMA; and   a host DMA configured to read the data stored in the buffer memory and output the read data to a host,   wherein a first operation of storing the data temporarily stored in the memory device in the buffer memory and a second operation of outputting the data stored in the buffer memory to the host are performed in parallel,   wherein, during the first operation, when a portion of the data from the flash DMA is output, the buffer memory secures a space for storing the data output from the flash DMA.   
     
     
         2 . The memory system of  claim 1 , wherein the controller further includes:
 a flash control circuit configured to control the flash DMA;   a host control circuit configured to control the host DMA; and   a buffer control circuit configured to control the buffer memory.   
     
     
         3 . The memory system of  claim 2 , wherein, in the first operation, the flash DMA receives the data temporarily stored in the memory device as at least one data group, each of a size of a read transmission unit, divides the at least one data group into multiple data sub-groups, each having a data size smaller than that of the read transmission unit, and transmits the multiple data sub-groups to the buffer memory. 
     
     
         4 . The memory system of  claim 3 , wherein the flash DMA:
 sequentially transmits the multiple data sub-groups to the buffer memory; and   outputs, to the buffer control circuit, read start information indicating that read streaming has been started when a first data sub-group, among the multiple data sub-groups, is transmitted to the buffer memory.   
     
     
         5 . The memory system of  claim 4 , wherein the buffer control circuit includes a schedule engine, and the schedule engine controls the buffer memory to secure a storage space of the multiple data sub-groups to be received from the flash DMA in response to the read start information. 
     
     
         6 . The memory system of  claim 5 , wherein the schedule engine is implemented with a Tomasulo algorithm or Scoreboard algorithm. 
     
     
         7 . The memory system of  claim 4 , wherein the flash DMA outputs a completion signal for the first operation to the flash control circuit when the first data sub-group is transmitted to the buffer memory. 
     
     
         8 . The memory system of  claim 7 , wherein the flash control circuit outputs data storage space position information to the host control circuit in response to the completion signal. 
     
     
         9 . The memory system of  claim 8 , wherein the host control circuit controls the host DMA to read the multiple data sub-groups stored in the buffer memory in response to the data storage space position information and output the multiple data sub-groups to the host. 
     
     
         10 . The memory system of  claim 9 , wherein the buffer memory is controlled in the second operation such that only a data sub-group which has been completely stored in the buffer memory, among the multiple data sub-groups, is read and output. 
     
     
         11 . The memory system of  claim 3 , wherein the first operation on all of the multiple data sub-groups except the first data sub-group and the second operation on all of the multiple data sub-groups except the last data sub-group are performed in parallel. 
     
     
         12 . A memory system comprising:
 a memory device configured to store data;   a host interface coupled to a host;   a buffer memory coupled between the memory device and the host interface;   a first controller configured to read data stored in the memory device and transmit the read data to the buffer memory; and   a second controller configured to output data stored in the buffer memory to the host through the host interface,   wherein a first operation of transmitting, by the first controller, the read data to the buffer memory and a second operation of outputting, by the second controller, the data stored in the buffer memory to the host are performed in parallel.   
     
     
         13 . The memory system of  claim 12 , wherein the first controller includes:
 a flash DMA configured to receive the data temporarily stored in the memory device in the first operation as at least one data group, each of a size of a read transmission unit, divides the at least one data group into multiple data sub-groups, each having a data size smaller than that of the read transmission unit, and transmits the multiple data sub-groups to the buffer memory; and   a flash control circuit configured to control the flash DMA.   
     
     
         14 . The memory system of  claim 13 , wherein the second controller includes:
 a host DMA configured to read the multiple data sub-groups stored in the buffer memory and output the multiple data sub-groups to the host; and   a host control circuit configured to control the host DMA.   
     
     
         15 . The memory system of  claim 14 , wherein the flash DMA sequentially transmits the multiple data sub-groups to the buffer memory, and
 the host DMA sequentially reads the multiple data sub-groups stored in the buffer memory and outputs the multiple data sub-groups to the host, after a first data sub-group among the multiple data sub-groups is transmitted to the buffer memory to be stored in the buffer memory.   
     
     
         16 . The memory system of  claim 15 , wherein the buffer memory includes a buffer control circuit configured to secure a storage space for the multiple data sub-groups to be received from the flash DMA, when the first data sub-group is transmitted to the buffer memory to be stored in the buffer memory. 
     
     
         17 . A method for operating a memory system, the method comprising:
 dividing data read from a memory device into multiple data sub-groups;   performing a first operation of sequentially transmitting the multiple data sub-groups to a buffer memory and storing the multiple data sub-groups in the buffer memory; and   performing a second operation of reading data stored in the buffer memory and outputting the read data to a host, when a first data sub-group among the multiple data sub-groups is completely stored in the buffer memory,   wherein the first operation and the second operation are performed in parallel.   
     
     
         18 . The method of  claim 17 , wherein the dividing of the read data into the multiple data sub-groups includes:
 receiving at least one data group as a read transmission unit from the memory device; and   dividing the at least one data group into the multiple data sub-groups, each having a data size smaller than that of the read transmission unit.   
     
     
         19 . The method of  claim 17 , wherein the first operation on all of the multiple data sub-groups except the first data sub-group and the second operation on all of the multiple data sub-groups except the last data sub-group are performed in parallel. 
     
     
         20 . The method of  claim 17 , wherein, when the first data sub-group is transmitted to the buffer memory, a space for storing the multiple data sub-groups in the buffer memory is secured.