Dynamic core selection for heterogeneous multi-core systems

Abstract

Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

1 . A multi-core computer system comprising:
 a first processor core of a first type to execute a program code that includes a user-supplied hint indicative of which processor core of the multi-core computer system the program code should be executed on   a second processor core of a second type different from the first type; and   circuitry to (i) monitor performance of the execution of the program code by the first processor core, (ii) determine, based on the performance of execution of the program code by the first processor core and the user-supplied hint, whether a predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core, and (iii) migrate execution of the program code from the first processor core to the second processor core in response to a determination that the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core.   
     
     
         2 . The multi-core computer system of  claim 1 , wherein to determine whether the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core comprises to ignore the user-supplied hint. 
     
     
         3 . The multi-core computer system of  claim 1 , wherein to determine whether the predicted performance of execution of the program code by the second processor is better than the performance of execution of the program code by the first processor core comprises to profile the program code to generate the user-supplied hint. 
     
     
         4 . The multi-core computer system of  claim 1 , wherein circuitry is further to:
 monitor, subsequent to the migration of execution of the program code to the second processor core, the performance of the execution of the program code by the second processor core;   determine, based on the performance of execution of the program code by the second processor core and the user-supplied hint, whether the performance of execution of the program code by the first processor core is better than the performance of execution of the program code by the second processor core; and   migrate execution of the program code from the second processor core back to the first processor core in response to a determination that the performance of execution of the program code by the first processor core is better than the performance of execution of the program code by the second processor core.   
     
     
         5 . The multi-core computer system of  claim 1 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core. 
     
     
         6 . The multi-core computer system of  claim 1 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core. 
     
     
         7 . The multi-core computer system of  claim 1 , wherein the circuitry is further to power up the second processor core in response to a determination that the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core. 
     
     
         8 . The multi-core computer system of  claim 1 , wherein the circuitry is further to power down the first processor core in response to a migration in execution of the program code from the first processor core to the second processor core. 
     
     
         9 . A method comprising:
 executing, by a multi-core computer system, program code on a first processor core of the multi-core computer system, wherein the first processor core is of a first type different from a second type of a second processor core of the multi-core computer system and wherein the program code includes a user-supplied hint indicative of which processor core of the multi-core computer system the program code should be executed on;   monitoring, by the multi-core computer system, performance of the execution of the program code by the first processor core;   determining, by the multi-core computer system and based on the performance of execution of the program code by the first processor core and the user-supplied hint, whether a predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core; and   migrating, by the multi-core computer system, execution of the program code from the first processor core to the second processor core in response to determining that the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core.   
     
     
         10 . The method of  claim 9 , wherein determining whether the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core comprises ignoring the user-supplied hint. 
     
     
         11 . The method of  claim 9 , wherein determining whether the predicted performance of execution of the program code by the second processor is better than the performance of execution of the program code by the first processor core comprises profiling the program code to generate the user-supplied hint. 
     
     
         12 . The method of  claim 9 , further comprising:
 monitoring, by the multi-core computer system and subsequent to the migration of execution of the program code to the second processor core, the performance of the execution of the program code by the second processor core;   determining, by the multi-core computer system and based on the performance of execution of the program code by the second processor core and the user-supplied hint, whether the performance of execution of the program code by the first processor core is better than the performance of execution of the program code by the second processor core; and   migrating, by the multi-core computer system, execution of the program code from the second processor core back to the first processor core in response to a determination that the performance of execution of the program code by the first processor core is better than the performance of execution of the program code by the second processor core.   
     
     
         13 . The method of  claim 9 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core. 
     
     
         14 . The method of  claim 9 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core. 
     
     
         15 . The method of  claim 9 , further comprising powering up the second processor core in response to a determination that the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core. 
     
     
         16 . The method of  claim 9 , further comprising powering down the first processor core in response to a migration in execution of the program code from the first processor core to the second processor core. 
     
     
         17 . One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to execution by a multi-core computer system, causes the multi-core computer system to:
 execute program code on a first processor core of the multi-core computer system, wherein the first processor core is of a first type different from a second type of a second processor core of the multi-core computer system and wherein the program code includes a user-supplied hint indicative of which processor core of the multi-core computer system the program code should be executed on;   monitor performance of the execution of the program code by the first processor core;   determine, based on the performance of execution of the program code by the first processor core and the user-supplied hint, whether a predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core; and   migrate execution of the program code from the first processor core to the second processor core in response to a determination that the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core.   
     
     
         18 . The one or more machine-readable storage media of  claim 17 , wherein to determine whether the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core comprises to ignore the user-supplied hint. 
     
     
         19 . The one or more machine-readable storage media of  claim 17 , wherein to determine whether the predicted performance of execution of the program code by the second processor is better than the performance of execution of the program code by the first processor core comprises to profile the program code to generate the user-supplied hint. 
     
     
         20 . The one or more machine-readable storage media of  claim 17 , wherein the plurality of instructions, when executed further cause the multi-core computer system to:
 monitor, subsequent to the migration of execution of the program code to the second processor core, the performance of the execution of the program code by the second processor core;   determine, based on the performance of execution of the program code by the second processor core and the user-supplied hint, whether the performance of execution of the program code by the first processor core is better than the performance of execution of the program code by the second processor core; and   migrate execution of the program code from the second processor core back to the first processor core in response to a determination that the performance of execution of the program code by the first processor core is better than the performance of execution of the program code by the second processor core.   
     
     
         21 . The one or more machine-readable storage media of  claim 17 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core. 
     
     
         22 . The one or more machine-readable storage media of  claim 17 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core. 
     
     
         23 . The one or more machine-readable storage media of  claim 17 , wherein the plurality of instructions, when executed further cause the multi-core computer system to power up the second processor core in response to a determination that the predicted performance of execution of the program code by the second processor core is better than the performance of execution of the program code by the first processor core. 
     
     
         24 . The one or more machine-readable storage media of  claim 17 , wherein the plurality of instructions, when executed further cause the multi-core computer system to power down the first processor core in response to a migration in execution of the program code from the first processor core to the second processor core.