Technologies for scalable packet reception and transmission

Abstract

Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.

1 . A network device to process packets, the network device comprising:
 one or more processors that include a plurality of cores;   a network interface controller (NIC) coupled to the one or more processors; and   one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the network device to:
 establish a ring in a memory of the one or more memory devices, wherein the ring is defined as a circular buffer and includes a plurality of slots to store entries representative of packets; 
 generate and assign receive descriptors to the slots in the ring, wherein each receive descriptor includes a pointer to a corresponding memory buffer to store packet data; 
 determine whether the NIC has received one or more packets; and 
 copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring. 
   
     
     
         2 . The network device of  claim 1 , wherein to generate and assign the receive descriptors to the slots in the ring comprises to generate and assign the receive descriptors with one or more of the cores. 
     
     
         3 . The network device of  claim 1 , wherein to generate and assign the receive descriptors to the slots in the ring comprises to generate and assign the receive descriptors with one or more hardware components of the NIC. 
     
     
         4 . The network device of  claim 1 , wherein to generate and assign the receive descriptors to the slots in the ring comprises to generate and assign the receive descriptors using multiple instances of an input stage executed as separate threads. 
     
     
         5 . The network device of  claim 4 , wherein the plurality of instructions, when executed by the one or more processors, further cause the network device to coordinate access of the multiple instances of the input stage to the slots with a modulo function. 
     
     
         6 . The network device of  claim 1 , wherein the plurality of instructions, when executed by the one or more processors, further cause the network device to identify available receive descriptors in the ring before the packet data is copied from the NIC, and
 wherein to copy the packet data from the NIC comprises to copy the packet data from the NIC to the memory buffers associated with the identified available receive descriptors.   
     
     
         7 . The network device of  claim 6 , wherein to identify the available receive descriptors comprises to identify the available receive descriptors with one or more of the cores. 
     
     
         8 . The network device of  claim 6 , wherein to identify the available receive descriptors comprises to identify the available receive descriptors with one or more hardware components of the NIC. 
     
     
         9 . The network device of  claim 6 , wherein to identify the available receive descriptors comprises to sequentially iterate through each slot in the ring and analyze metadata stored in association with each slot for an indication that one or more of the receive descriptors is available. 
     
     
         10 . The network device of  claim 1 , wherein the plurality of instructions, when executed by the one or more processors, further cause the network device to copy the receive descriptors from the ring to a NIC receive queue before the determination of whether the NIC has received one or more packets. 
     
     
         11 . The network device of  claim 1 , wherein to determine whether the NIC has received one or more packets comprises to poll the NIC with one or more of the cores. 
     
     
         12 . The network device of  claim 1 , wherein the plurality of instructions, when executed by the one or more processors, further cause the network device to:
 generate and assign transmit descriptors to the slots in the ring, wherein each transmit descriptor includes a pointer to a corresponding memory buffer where packet data to be transmitted is stored;   identify transmit descriptors for slots of the ring associated with packet data that has been marked as ready to transmit;   copy, with DMA, packet data from the memory buffers associated with the identified transmit descriptors to the NIC for transmission.   
     
     
         13 . One or more machine-readable storage media comprising a plurality of instructions stored thereon that in response to being executed, cause a network device to:
 establish a ring in a memory of the network device, wherein the ring is defined as a circular buffer and includes a plurality of slots to store entries representative of packets;   generate and assign receive descriptors to the slots in the ring, wherein each receive descriptor includes a pointer to a corresponding memory buffer to store packet data;   determine whether a network interface controller (NIC) of the network device has received one or more packets; and   copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.   
     
     
         14 . The one or more machine-readable storage media of  claim 13 , wherein to generate and assign the receive descriptors to the slots in the ring comprises to generate and assign the receive descriptors with one or more cores of a processor of the network device. 
     
     
         15 . The one or more machine-readable storage media of  claim 13 , wherein to generate and assign the receive descriptors to the slots in the ring comprises to generate and assign the receive descriptors with one or more hardware components of the NIC. 
     
     
         16 . The one or more machine-readable storage media of  claim 13 , wherein to generate and assign the receive descriptors to the slots in the ring comprises to generate and assign the receive descriptors using multiple instances of an input stage executed as separate threads. 
     
     
         17 . The one or more machine-readable storage media of  claim 16 , wherein the plurality of instructions further cause the network device to coordinate access of the multiple instances of the input stage to the slots with a modulo function. 
     
     
         18 . The one or more machine-readable storage media of  claim 13 , wherein the plurality of instructions further cause the network device to identify available receive descriptors in the ring before the packet data is copied from the NIC, and
 wherein to copy the packet data from the NIC comprises to copy the packet data from the NIC to the memory buffers associated with the identified available receive descriptors.   
     
     
         19 . The one or more machine-readable storage media of  claim 18 , wherein to identify the available receive descriptors comprises to identify the available receive descriptors with one or more cores of a processor of the network device. 
     
     
         20 . The one or more machine-readable storage media of  claim 18 , wherein to identify the available receive descriptors comprises to identify the available receive descriptors with one or more hardware components of the NIC.