Semiconductor memory

Abstract

A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

What is claimed is: 
     
         1 . A semiconductor memory comprising:
 a substrate;   a source line layer above the substrate in a memory region and a peripheral region of the substrate;   a first insulating layer above the source line layer in the memory and peripheral regions;   a first conductive layer on the first insulating layer in the memory and peripheral regions;   an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region; and   a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region, a bottom end of each of the pillars being in the source line layer in a thickness direction,   wherein a carrier density of the source line layer in the memory region is higher than a carrier density of the source line layer in the peripheral region.   
     
     
         2 . The semiconductor memory according to  claim 1 , wherein
 each of the plurality of pillars includes a first insulator extending in a stack direction of the second insulating layer and the second conductive layers, and a first semiconductor covering bottom and side surfaces of the first insulator, and   the source line layer is in contact with the first semiconductor of each of the pillars on the side surface of each of the pillars.   
     
     
         3 . The semiconductor memory according to  claim 1 , further comprising:
 an insulating wall extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region, the insulating wall also extending in a surface direction of the substrate, and a bottom end of the insulating wall being located in the source line layer in the thickness direction.   
     
     
         4 . The semiconductor memory according to  claim 1 , wherein the source line layer includes first to fifth layers stacked in order from a substrate side, and both the second layer and the fourth layer contain an oxide or a nitride. 
     
     
         5 . The semiconductor memory according to  claim 4 , wherein a thickness of both the second layer and the fourth layer is 2 nm or less. 
     
     
         6 . The semiconductor memory according to  claim 1 , wherein the source line layer in the memory region contains phosphorus. 
     
     
         7 . The semiconductor memory according to  claim 1 , wherein the source line layer in the peripheral region contains germanium. 
     
     
         8 . The semiconductor memory according to  claim 1 , wherein the source line layer contains carbon. 
     
     
         9 . The semiconductor memory according to  claim 1 , wherein the source line layer contains nitrogen or oxygen. 
     
     
         10 . The semiconductor memory according to  claim 1 , wherein the source line layer contains boron. 
     
     
         11 . A semiconductor memory comprising:
 a substrate;   a source line layer above the substrate in a memory region and a peripheral region of the substrate;   an insulating layer above the source line layer in the memory and peripheral regions;   a select gate line layer on the insulating layer in the memory and peripheral regions;   a plurality of word line layers on the select gate line layer in the memory region; and   a plurality of pillars extending through the word line layers, the select gate line layer, and the insulating layer in the memory region, a bottom end of each of the pillars being in the source line layer in a thickness direction,   wherein a carrier density of the source line layer in the memory region is higher than a carrier density of the source line layer in the peripheral region.   
     
     
         12 . The semiconductor memory according to  claim 11 , wherein
 each of the plurality of pillars includes a first insulator extending in the thickness direction and a first semiconductor covering bottom and side surfaces of the first insulator, and   the source line layer is in contact with the first semiconductor of each of the pillars on the side surface of each of the pillars.   
     
     
         13 . The semiconductor memory according to  claim 11 , further comprising:
 an insulating wall extending through the word line layers, the select gate line layer, and the insulating layer in the memory region, the insulating wall also extending in a surface direction of the substrate, and a bottom end of the insulating wall being located in the source line layer in the thickness direction.   
     
     
         14 . The semiconductor memory according to  claim 11 , wherein the source line layer includes first to fifth layers stacked in order from a substrate side, and both the second layer and the fourth layer contain an oxide or a nitride. 
     
     
         15 . The semiconductor memory according to  claim 14 , wherein a thickness of both the second layer and the fourth layer is 2 nm or less. 
     
     
         16 . The semiconductor memory according to  claim 11 , wherein the source line layer in the memory region contains phosphorus. 
     
     
         17 . The semiconductor memory according to  claim 11 , wherein the source line layer in the peripheral region contains germanium. 
     
     
         18 . The semiconductor memory according to  claim 11 , wherein the source line layer contains carbon. 
     
     
         19 . The semiconductor memory according to  claim 11 , wherein the source line layer contains nitrogen or oxygen. 
     
     
         20 . The semiconductor memory according to  claim 11 , wherein the source line layer contains boron.