Semiconductor devices and methods of making the same

Abstract

Various leadframe implementations may include a conductive substrate electrically coupled to a first lead where the conductive substrate includes a first elevated region and a second elevated region on a first side of the conductive substrate. The first elevated region may include a first planar surface and the second elevated region may include a second planar surface on the first side of the conductive substrate. Various implementations may include where the first planar surface of the first elevated region and the second planar surface of the second elevated region are configured to attach to a contact pad of a semiconductor die. The first planar surface may include a curved edge. The second planar surface may include a polygonal shape. The curved edge of the first planar surface may be configured to laterally align with a curved edge of the contact pad of the semiconductor die.

What is claimed is: 
     
         1 . A leadframe comprising:
 a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate;   wherein the first planar surface of the first elevated region and the second planar surface of the second elevated region are configured to attach to a contact pad of a semiconductor die;   wherein the first planar surface comprises a curved edge;   wherein the second planar surface has a polygonal shape; and   wherein the curved edge of the first planar surface is configured to laterally align with a curved edge of the contact pad of the semiconductor die.   
     
     
         2 . The leadframe of  claim 1 , wherein the conductive substrate comprises at least 10 elevated regions. 
     
     
         3 . The leadframe of  claim 1 , wherein the conductive substrate is at least partially encapsulated in a molding material. 
     
     
         4 . The leadframe of  claim 1 , wherein the second planar surface of the second elevated region has a first corner that is laterally aligned with a first corner of the contact pad. 
     
     
         5 . The leadframe of  claim 1 , wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate;
 wherein the third elevated comprises a third planar surface on the first side of the conductive substrate; and   wherein the third planar surface of the third elevated region is configured to attach to the contact pad of the semiconductor die.   
     
     
         6 . The leadframe of  claim 5 , wherein the third planar surface has a polygonal shape with different dimensions than the polygonal shape of the second planar surface. 
     
     
         7 . The leadframe of  claim 1 , wherein the first planar surface of the first elevated region is rectangular. 
     
     
         8 . The leadframe of  claim 1 , wherein the conductive substrate comprises at least six elevated regions on the first side of the conductive; and
 wherein each of the at least six elevated regions comprise a planar surface that is configured to attach to the contact pad of the semiconductor die.   
     
     
         9 . A leadframe comprising:
 a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate;   wherein the first planar surface of the first elevated region and the second planar surface of the second elevated region are both configured to be soldered to a contact pad of a semiconductor die; and   wherein only a portion of the first planar surface is configured to be soldered to the contact pad of the semiconductor die.   
     
     
         10 . The leadframe of  claim 9 , wherein the conductive substrate comprises at least 10 elevated regions. 
     
     
         11 . The leadframe of  claim 9 , wherein the second planar surface of the second elevated region has a first corner that is laterally aligned with a first corner of the contact pad. 
     
     
         12 . The leadframe of  claim 9 , wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate;
 wherein the third elevated comprises a third planar surface on the first side of the conductive substrate; and   wherein the third planar surface of the third elevated region is configured to be attached to the contact pad of the semiconductor die.   
     
     
         13 . The leadframe of  claim 12 , wherein the third planar surface has a polygonal shape with different dimensions than the polygonal shape of the second planar surface. 
     
     
         14 . The leadframe of  claim 9 , wherein the first planar surface of the first elevated region is rectangular. 
     
     
         15 . The leadframe of  claim 9 , wherein the conductive substrate comprises at least six elevated regions on the first side of the conductive; and
 wherein each of the at least six elevated regions comprise a planar surface that is configured to attach to the contact pad of the semiconductor die.   
     
     
         16 . A leadframe comprising:
 a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate; and   wherein the conductive substrate is configured to electrically couple to a first contact pad of a semiconductor die and is further configured to solder to both the first planar surface of the first elevated region and the second planar surface of the second elevated region;   wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region; and   wherein the first planar surface of the first elevated region has a first corner that is configured to laterally align with a first corner of the first contact pad.   
     
     
         17 . The leadframe of  claim 16 , wherein the conductive substrate comprises at least 10 elevated regions. 
     
     
         18 . The leadframe of  claim 16 , wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate;
 wherein the third elevated comprises a third planar surface on the first side of the conductive substrate; and   wherein the third planar surface of the third elevated region is configured to attach to the contact pad.   
     
     
         19 . The leadframe of  claim 18 , wherein the third planar surface has a polygonal shape with different dimensions than the polygonal shape of the second planar surface. 
     
     
         20 . The leadframe of  claim 16 , wherein the conductive substrate comprises at least six elevated regions on the first side of the conductive; and
 wherein each of the at least six elevated regions comprise a planar surface that is configured to attach to the contact pad of the semiconductor die.