Delay time calibration of optical distance measurement devices, and associated systems and methods

Abstract

Representative embodiments of the present technology include a device for measuring distance to an object. The device comprises a light emitter configured to emit an outbound light pulse and a light sensor configured to receive a returning light pulse and output a pulse signal representing the returning light pulse. The device further comprises a field-programmable gate array (FPGA) coupled to the light sensor and including a time-to-digital converter (TDC) having a series of sequentially coupled delay units. Individual sequentially coupled delay units are associated with corresponding individual delay times. At least some of the sequentially coupled delay units have different individual delay times. The TDC is configured to measure timing information of the pulse signal based at least in part on the individual delay times of the sequentially coupled delay units. The device further includes a controller configured to calculate the distance to the object based on the timing information.

1 . A device for measuring distance to an object, the device comprising:
 a light emitter configured to emit an outbound light pulse;   a light sensor configured to receive a returning light pulse reflected from the object and output a pulse signal representing the returning light pulse;   a field-programmable gate array (FPGA) coupled to the light sensor and including a time-to-digital converter (TDC) having a series of sequentially coupled delay units, individual sequentially coupled delay units associated with corresponding individual delay times, wherein at least some of the sequentially coupled delay units are configured using the logic components within the FPGA, wherein at least some of the sequentially coupled delay units have different individual delay times, and wherein the TDC is configured to measure timing information of the pulse signal based at least in part on the individual delay times of the sequentially coupled delay units; and   a controller configured to calculate the distance to the object based on the timing information.   
     
     
         2 . The device of  claim 1  wherein the light emitter, light sensor, FPGA, and controller are carried by an unmanned aerial vehicle, an autonomous vehicle, or a robot. 
     
     
         3 . The device of  claim 1  wherein the TDC is configured to measure the timing information by:
 propagating an input signal through the series of sequentially coupled delay units, the input signal corresponding to one or more portions of the pulse signal; 
 determining a fine time value for the input signal using the series of sequentially coupled delay units; and 
 determining a coarse time value for the input signal based on a number of elapsed clock cycles of the FPGA. 
 
     
     
         4 . The device of  claim 3  wherein the fine time value corresponds to a sum of the individual delay times of a subset of the series of sequentially coupled delay units that receives the input signal prior to a next clock cycle of the FPGA. 
     
     
         5 . The device of  claim 3  wherein the timing information corresponds to a difference between the coarse time value and the fine time value. 
     
     
         6 . The device of  claim 3  wherein a time resolution of the fine time value is higher than a time resolution of the coarse time value. 
     
     
         7 . The device of  claim 1  wherein the series of sequentially coupled delay units includes at least 25 delay units. 
     
     
         8 . The device of  claim 1  wherein the series of sequentially coupled delay units includes a carry chain or a lookup table (LUT). 
     
     
         9 . The device of  claim 1  wherein the individual delay times are within a range from 5 picoseconds to 2000 picoseconds. 
     
     
         10 . (canceled) 
     
     
         11 . The device of  claim 1  wherein the TDC includes a latch unit having a plurality of latches, individual latches being coupled to corresponding sequential delay units, and wherein the TDC is configured to:
 propagate an input signal through the series of sequentially coupled delay units, the input signal corresponding to one or more portions of the pulse signal; 
 determine a fine time value for the input signal using the series of sequentially coupled delay units, wherein the fine time value corresponds to a sum of the individual delay times of a subset of the series of sequentially coupled delay units that receives the input signal prior to a next clock cycle of the FPGA; 
 determine a coarse time for the input signal measurement based on a number of elapsed clock cycles of the FPGA; and 
 measure the timing information based on a difference between the coarse time value and the fine time value. 
 
     
     
         12 .- 20 . (canceled) 
     
     
         21 . A method, comprising:
 installing, in an optical distance measurement device, a field-programmable gate array (FPGA) including a time-to-digital converter (TDC), the TDC including a series of sequentially coupled delay units, wherein the FPGA has been calibrated in accordance with the following method:
 receiving, at the series of sequentially coupled delay units, a plurality of calibration signals; and 
 determining an individual delay time for corresponding sequentially coupled delay units, wherein an individual delay time corresponds to a count representing a number of times the corresponding delay unit is last in the series of sequentially coupled delay units to receive a calibration signal prior to a next clock cycle of the FPGA. 
   
     
     
         22 . The method of  claim 21 , further comprising installing the optical distance measurement device in an unmanned vehicle, an autonomous vehicle, or a robot. 
     
     
         23 . The method of  claim 21 , further comprising calibrating the FPGA by:
 receiving, at the series of sequentially coupled delay units, the plurality of calibration signals; and   determining the individual delay time for corresponding sequentially coupled delay units.   
     
     
         24 . The method of  claim 23  wherein the plurality of calibration signals includes a plurality of randomized signals. 
     
     
         25 . The method of  claim 24  wherein the plurality of randomized signals are randomized with respect to a clock signal of the FPGA. 
     
     
         26 . The method of  claim 23  wherein at least some of the sequentially coupled delay units have different individual delay times. 
     
     
         27 . The method of  claim 23  wherein the individual delay time for a corresponding delay unit is proportional to the count for the delay unit. 
     
     
         28 . The method of  claim 23 , further comprising calculating the individual delay time based at least in part on a ratio representing the count of the corresponding delay unit divided by a sum of the counts of each of the sequentially coupled delay units. 
     
     
         29 . The method of  claim 23 , further comprising propagating the plurality of calibration signals through the series of sequentially coupled delay units. 
     
     
         30 . The method of  claim 29 , further comprising latching outputs of the series of sequentially coupled delay units using a plurality of latches as a calibration signal propagates through the series of sequentially coupled delay units. 
     
     
         31 . The method of  claim 30 , further comprising using the latched outputs to identify a delay unit that is last in the series of sequentially coupled delay units to receive the calibration signal prior to the next clock cycle of the FPGA. 
     
     
         32 - 64 . (canceled)