Ultra-Low Power Static State Flip Flop

Abstract

At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

What is claimed is: 
     
         1 . A flip-flop, comprising:
 a tri-state inverter;   a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate, the master latch receives a clock signal;   a slave latch coupled to the master latch and comprising a second transistor and a second inverter, the slave latch receives the clock signal; and   an enablement logic coupled to the master latch and comprising multiple, additional logic gates,   wherein the tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.   
     
     
         2 . The flip-flop of  claim 1 , wherein the second transistor in the slave latch is an NMOS switch, and wherein the slave latch further comprises a second NMOS switch and a PMOS switch, a gate of the PMOS switch coupled to an output of the first logic gate, a node between the PMOS switch and the second NMOS switch coupled to the second inverter of the slave latch. 
     
     
         3 . A method, comprising:
 providing to a flip-flop an input signal D that is identical to an output signal Q of the flip-flop, the output signal Q having a first value;   providing a clock signal to the flip-flop at a first bit value;   passing the input signal D and the clock signal at the first bit value through a network of transistor switches, inverters, buffers, and logic gates such that the states of master and slave latches in the flip-flop hold the output signal Q at the first value;   toggling the clock signal to a second bit value; and   passing the input signal D and the clock signal at the second bit value through the network of transistor switches, inverters, buffers, and logic gates such that the states of the master and slave latches remain static.   
     
     
         4 . The method of  claim 3 , wherein the network comprises two PMOS switches, four NMOS switches, and a NAND gate. 
     
     
         5 . The method of  claim 4 , wherein the network further includes an AND gate and an OR gate, an output of the OR gate provided to the NAND gate. 
     
     
         6 . A flip-flop, comprising:
 a tri-state buffer;   a master latch coupled to the tri-state buffer and comprising a first transistor, a first inverter, and a first logic gate, the master latch receives a clock signal;   a slave latch coupled to the master latch and comprising a second transistor and a second inverter, the slave latch receives the clock signal; and   an enablement logic coupled to the master latch and comprising multiple, additional logic gates,   wherein the tri-state buffer, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.   
     
     
         7 . The flip-flop of  claim 6 , wherein the first transistor is an NMOS switch, and wherein the master latch further comprises a second NMOS switch coupled to the NMOS switch and a PMOS switch coupled to the second NMOS switch. 
     
     
         8 . The flip-flop of  claim 6 , wherein the multiple, additional logic gates in the enablement logic include an AND gate and an OR gate. 
     
     
         9 . The flip-flop of  claim 6 , wherein the first logic gate is a NAND gate. 
     
     
         10 . The flip-flop of  claim 6 , wherein the second transistor in the slave latch is an NMOS switch, and wherein the slave latch further comprises a second NMOS switch and a PMOS switch, a gate of the PMOS switch coupled to an output of the first logic gate, a node between the PMOS switch and the second NMOS switch coupled to the second inverter of the slave latch. 
     
     
         11 . The flip-flop of  claim 6 , wherein the slave latch further comprises a third inverter, an output of the third inverter couples to an input of another tri-state buffer.