US2019319585A1PendingUtilityA1

Dynamic error vector magnitude duty cycle correction

Assignee: SKYWORKS SOLUTIONS INCPriority: Sep 19, 2013Filed: Mar 14, 2019Published: Oct 17, 2019
Est. expirySep 19, 2033(~7.1 yrs left)· nominal 20-yr term from priority
H03F 1/0222H03F 2203/7209H04B 1/04H03F 2200/429H03F 1/0277H03F 2200/451H03F 3/217H03F 2200/387H03F 1/56H03F 2203/7221H03F 3/72H03F 2200/165H03F 2200/351H03F 2200/336H03F 2200/111H03F 3/195H03F 1/0266H03F 2203/7236H03F 3/245H03F 2200/555
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Claims

Abstract

Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A power amplifier system with dynamic error vector magnitude compensation, the power amplifier system comprising:
 a power amplifier configured to provide a radio frequency signal;   a duty cycle tracking circuit configured to generate a correction signal that is representative of a duty cycle of the power amplifier over time; and   a bias circuit configured to adjust a bias signal based on the correction signal such that the bias signal is larger for a lower duty cycle of the power amplifier than for a higher duty cycle of the power amplifier, and to bias the power amplifier using the bias signal so as to compensate for dynamic error vector magnitude.   
     
     
         3 . The power amplifier system of  claim 2  wherein the bias circuit includes a reference bipolar transistor and a base current helper bipolar transistor having an emitter electrically connected to a base of the reference bipolar transistor. 
     
     
         4 . The power amplifier system of  claim 2  wherein the bias circuit includes an adjustable current source configured to receive the correction signal, and the bias signal is a voltage signal that is generated using an output of the adjustable current source. 
     
     
         5 . The power amplifier system of  claim 2  wherein the radio frequency signal is a Wi-Fi signal. 
     
     
         6 . The power amplifier system of  claim 2  wherein the radio frequency signal is a wireless local area network signal. 
     
     
         7 . The power amplifier system of  claim 2  wherein the duty cycle tracking circuit includes an integrator configured to integrate an enable signal for the power amplifier. 
     
     
         8 . The power amplifier system of  claim 2  wherein the duty cycle tracking circuit includes an accumulator. 
     
     
         9 . The power amplifier system of  claim 2  wherein the duty cycle tracking circuit includes a decimator. 
     
     
         10 . The power amplifier system of  claim 2  wherein the duty cycle tracking circuit includes an up-down counter. 
     
     
         11 . A wireless communication device with dynamic error vector magnitude compensation, the wireless communication device comprising:
 a power amplifier configured to provide a radio frequency signal;   a duty cycle tracking circuit configured to generate a correction signal that is representative of a duty cycle of the power amplifier over time;   a bias circuit configured to adjust a bias signal based on the correction signal such that the bias signal is larger for a lower duty cycle of the power amplifier than for a higher duty cycle of the power amplifier, and to bias the power amplifier using the bias signal so as to compensate for dynamic error vector magnitude;   an antenna configured to transmit the radio frequency signal; and   switches configured to selectively electrically couple an output of the power amplifier to the antenna.   
     
     
         12 . The wireless communication device of  claim 11  wherein the power amplifier is included on a first die, the duty cycle tracking circuit is included on a second die, and a packaged power amplifier module includes the first die and the second die. 
     
     
         13 . The wireless communication device of  claim 11  wherein the wireless communication device is a mobile phone. 
     
     
         14 . A method of amplifier biasing with dynamic error vector magnitude compensation, the method comprising:
 generating a correction signal that is representative of a duty cycle of an amplifier over time;   adjusting a bias signal based on the correction signal such that the bias signal is larger for a lower duty cycle of the amplifier than for a higher duty cycle of the amplifier; and   biasing the amplifier with the bias signal so as to compensate for change in a parameter of the amplifier due to a change in the duty cycle of the amplifier.   
     
     
         15 . The method of  claim 14  further comprising amplifying a wireless local area network signal with the amplifier, the amplifier being a power amplifier. 
     
     
         16 . The method of  claim 14  further comprising transmitting, via an antenna of a mobile device, an amplified radio frequency provided by the amplifier. 
     
     
         17 . The method of  claim 14  wherein the parameter is a gain of the amplifier. 
     
     
         18 . The method of  claim 14  wherein the parameter is a phase of a radio frequency signal provided by the amplifier. 
     
     
         19 . The method of  claim 14  wherein the bias signal is a voltage signal that is generated based on an output of an adjustable current source that receives the correction signal. 
     
     
         20 . The method of  claim 14  wherein the generating includes low pass filtering an indication of the duty cycle of the amplifier. 
     
     
         21 . The method of  claim 14  wherein the generating includes integrating a binary signal indicative of the duty cycle of the amplifier.

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