US2019318966A1PendingUtilityA1

High k metal gate stack with single work-function metal

Assignee: IBMPriority: Mar 6, 2014Filed: Jun 27, 2019Published: Oct 17, 2019
Est. expiryMar 6, 2034(~7.6 yrs left)· nominal 20-yr term from priority
H10P 32/14H10D 64/01352H10D 64/01318H10D 64/0134H10D 84/83135H10D 84/8314H10D 64/667H10D 84/85H01L 21/28088H01L 21/28185H01L 29/66545H01L 27/092H01L 29/4966H01L 29/42372H01L 21/823857H01L 21/823842H01L 29/517H01L 21/28238H01L 21/823828H01L 21/225H10D 84/0181H10D 84/0177H10D 64/691H10D 64/517H10D 64/017H10D 84/0172H10D 84/038
60
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.

Claims

exact text as granted — not AI-modified
We claim: 
     
         1 . An integrated circuit comprising:
 a first gate of an N-FET and a second gate of a P-FET on a substrate, wherein the first gate and the second gate each have a gate opening width of less than 20 nanometers;   a work function metal lining both the first gate opening and the second gate opening;   a high dielectric material between the work function metal and the substrate wherein the high dielectric material is doped with an n-dopant in the first gate and is doped with a p-dopant in the second gate; and   a bulk fill material filling a remainder of the gate opening.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the work function metal is a titanium nitride layer having a thickness from about 25 angstroms to about 50 angstroms. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the high dielectric material lines the sidewalls of the first gate opening and the second gate opening. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the high dielectric material includes an interfacial layer. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the p-dopant is aluminum. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the n-dopant is lanthanum. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the bulk fill material comprises tungsten. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the width of the bulk fill material is about 20 to about 70% of the width of the gate opening in each of the first and second gates. 
     
     
         9 . The integrated circuit of  claim 1 , wherein a width of the bulk fill material is about 20 percent to about 50 percent of the width of the gate opening in each of the first gate and the second gate, and wherein the gate opening width is less than about 17 nanometers. 
     
     
         10 . An integrated circuit having an N-FET metal gate and a P-FET metal gate sharing the same work function metal, the integrated circuit comprising:
 an n-doped high dielectric constant material only along a bottom of a first opening in a dielectric layer, the n-doped high dielectric constant material is in direct contact with a portion of a substrate exposed at the bottom of the first opening;   a p-doped high dielectric constant material only along a bottom of a second opening in the dielectric layer, the p-doped high dielectric constant material is in direct contact with a portion of the substrate exposed at the bottom of the second opening;   a work function metal above and in direct contact with the p-doped high dielectric constant material and the n-doped high dielectric constant material; and   a bulk fill material directly on top of the work function metal, wherein a width of the bulk fill material comprises more than about 30% of the width of each of the first opening and the second opening, wherein the work function metal is less than about 40 angstroms thick, and wherein the width of the first opening and the second opening are each less than 20 nanometers.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the p-doped high dielectric constant material comprises aluminum. 
     
     
         12 . The integrated circuit of  claim 10 , wherein the n-doped high dielectric constant material comprises lanthanum. 
     
     
         13 . The integrated circuit of  claim 10 , wherein an effective work function of the N-FET metal gate is a combination of an inherent work function of the work function metal and the additional work function reduction caused by n-dopants of the n-doped high dielectric constant material, and an effective work function of the P-FET metal gate is a combination of an inherent work function of the work function metal and the additional work function increase caused by p-dopants of the p-doped high dielectric constant material. 
     
     
         14 . A integrated circuit comprising:
 an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening;   a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening;   a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer; and   a bulk fill material above and in direct contact with the shared work function metal.   
     
     
         15 . The integrated circuit of  claim 14 , wherein the first opening is in an N-FET region of the substrate and the second opening is in a P-FET region of the substrate. 
     
     
         16 . The integrated circuit of  claim 14 , wherein the p-doped high-k dielectric layer comprises aluminum. 
     
     
         17 . The integrated circuit of  claim 14 , wherein the n-doped high-k dielectric layer comprises lanthanum. 
     
     
         18 . The integrated circuit of  claim 14 , wherein the shared work function metal comprises titanium nitride and the bulk fill material comprises tungsten. 
     
     
         19 . The integrated circuit of  claim 14 , wherein a width of the first opening and the second opening are each less than 20 nanometers, a thickness of the shared work function metal is less than about 40 angstroms, and a width of the bulk fill material is more than 45% of the width of each of the first opening and the second opening.

Join the waitlist — get patent alerts

Track US2019318966A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.