Circuit for meeting setup and hold times of a control signal with respect to a clock

Abstract

A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

What is claimed is: 
     
         1 . A circuit, comprising:
 a plurality of series-coupled delay buffers;   a plurality of logic gates, each logic gate including first and second inputs, the first input of each logic gate is coupled to a corresponding one of the delay buffers; and   a plurality of flip-flops, each flip-flop including a data input and a data output, the data input coupled to an output of a corresponding one of the logic gates and the data output coupled to the second input of one of the corresponding logic gates.   
     
     
         2 . The circuit of  claim 1 , wherein each of the plurality of flip-flops is a D flip-flop. 
     
     
         3 . The circuit of  claim 1 , wherein each of the plurality of flips includes a clock input coupled to receive a common clock. 
     
     
         4 . The circuit of  claim 1 , wherein the plurality of delay buffers includes at least five delay buffers.