Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

1 .- 39 . (canceled) 
     
     
         40 . A semiconductor device, comprising:
 a lower wire on a substrate;   an etch stop layer on the lower wire, the etch stop layer including a first etch stop pattern, a second etch stop pattern and a third etch stop pattern, the second etch stop pattern disposed between the first and third etch stop patterns, the first and third etch stop patterns including a same material and the second etch stop pattern including a carbon element;   an interlayer insulating layer on the etch stop layer;   a via in the etch stop layer and the interlayer insulating layer; and   an upper wire on the via, the upper wire having a bottommost surface and a topmost surface,   wherein a width of the topmost surface of the upper wire is greater than a width of the bottommost surface of the upper wire.   
     
     
         41 . The semiconductor device of  claim 40 , wherein the upper wire is disposed in the interlayer insulating layer and wherein the via includes a first portion in the first etch stop pattern, a second portion in the second etch stop pattern, a third portion in the third etch stop pattern, and a fourth portion in the interlayer insulating layer. 
     
     
         42 . The semiconductor device of  claim 41 , wherein a width of second portion of the via is greater than a width of the first portion of the via, and the width of the second portion of the via is smaller than a width of the third portion of the via. 
     
     
         43 . The semiconductor device of  claim 42 , wherein the width of the third portion of the via is smaller than a width of the fourth portion of the via. 
     
     
         44 . The semiconductor device of  claim 43 , wherein the width of the fourth portion of the via is smaller than a width of the upper wire. 
     
     
         45 . The semiconductor device of  claim 41 , wherein a bottom surface of the fourth portion of the via covers a first portion of a top surface of the third etch stop pattern and a bottom surface of the interlayer insulating layer covers a second portion of the top surface of the third etch stop pattern. 
     
     
         46 . The semiconductor device of  claim 41 , wherein a top surface of the third portion of the via contacts a bottom surface of the fourth portion of the via, and a width of the top surface of the third portion is smaller than a width of the bottom surface of the fourth portion. 
     
     
         47 . The semiconductor device of  claim 41 , wherein sidewalls of the first, second and third portions of the via have an acute angle with respect to an upper surface of the lower wire. 
     
     
         48 . The semiconductor device of  claim 41 , wherein a sidewall of the via has a step configuration such that a lateral edge of the third etch stop pattern is disposed closer to a center of the via than a lateral edge of the interlayer insulating layer and the fourth portion of the via covers the lateral edge of the third etch stop pattern. 
     
     
         49 . The semiconductor device of  claim 41 , wherein a slope of a sidewall of the first portion of the via, a slope of a sidewall of the second portion of the via and a slope of a sidewall of the third portion of the via are continuous. 
     
     
         50 . The semiconductor device of  claim 41 , wherein a slope of a sidewall of the fourth portion of the via is continuous with a slope of a sidewall of the upper wire. 
     
     
         51 . The semiconductor device of  claim 40 , wherein the via and the upper wire includes a same material. 
     
     
         52 . The semiconductor device of  claim 40 , wherein the second etch stop pattern includes one or more of oxide doped carbon and SiCN. 
     
     
         53 . A semiconductor device, comprising:
 a lower wire on a substrate;   an etch stop layer on the lower wire;   an interlayer insulating layer on the etch stop layer;   a via in the etch stop layer and the interlayer insulating layer, the via including a first portion in the etch stop layer and a second portion in the interlayer insulating layer; and   an upper wire on the via,   wherein a bottom surface of the second portion of the via covers a first portion of a top surface of the etch stop layer.   
     
     
         54 . The semiconductor device of  claim 53 , wherein the etch stop layer includes a first etch stop pattern, a second etch stop pattern and a third etch stop pattern, the second etch stop pattern disposed between the first and third etch stop patterns, the first and third etch stop patterns including a same material and the second etch stop pattern including a carbon element. 
     
     
         55 . The semiconductor device of  claim 53 , wherein a bottom surface of the interlayer insulating layer covers a second portion of the top surface of the etch stop layer. 
     
     
         56 . The semiconductor device of  claim 53 , wherein the first portion of the top surface of the etch stop layer is exposed by the interlayer insulating layer. 
     
     
         57 . The semiconductor device of  claim 53 , wherein the first portion of the top surface of the etch stop layer does not overlap the interlayer insulating layer. 
     
     
         58 . The semiconductor device of  claim 53 , wherein a sidewall of the via has a step configuration such that a lateral edge of the etch stop layer is disposed closer to a center of the via than a lateral edge of the interlayer insulating layer. 
     
     
         59 . The semiconductor device of  claim 53 , wherein a slope of a sidewall of the second portion of the via is continuous with a slope of a sidewall of the upper wire.