Survivability guarantees for memory traffic

Abstract

Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.

What is claimed is: 
     
         1 . A system for computer memory management, the system comprising:
 monitoring circuitry to produce a rate exceeded signal that indicates that memory traffic flow from a traffic source exceeds a threshold; and   rate control circuitry that includes throttle circuitry, the rate control circuitry to:
 receive the rate exceeded signal from the monitoring circuitry; 
 receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and 
 invoke the throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted. 
   
     
     
         2 . The system of  claim 1 , wherein the rate control circuitry includes a control signal to enable or disable the throttle circuitry regardless of whether the rate exceeded signal or the distress signal are asserted. 
     
     
         3 . The system of  claim 1 , wherein the monitoring circuitry uses a leaky-bucket algorithm to determine whether to assert the rate exceeded signal. 
     
     
         4 . The system of  claim 1 , wherein the monitoring circuitry includes a request counter to maintain a counter of how many requests are received in a time period. 
     
     
         5 . The system of  claim 4 , wherein the time period is a number of clock cycles. 
     
     
         6 . The system of  claim 5 , wherein the time period is measured using a time-window counter, the time-window counter configured to count down from a predetermined value at each clock cycle and cause the request counter to reset. 
     
     
         7 . The system of  claim 1 , wherein the rate control circuitry is configured to not throttle response traffic to the traffic source. 
     
     
         8 . The system of  claim 1 , wherein the throttle control circuitry implements a fixed throttle rate. 
     
     
         9 . The system of  claim 1 , wherein the throttle circuitry implements a variable throttle rate. 
     
     
         10 . The system of  claim 9 , wherein the variable throttle rate is a function of a number of active cores in a system. 
     
     
         11 . The system of  claim 1 , wherein the memory controller that interfaces with the memory device implements memory deduplication. 
     
     
         12 . A method of computer memory management, the method comprising:
 receiving a rate exceeded signal, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold;   receiving a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and   throttling the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.   
     
     
         13 . The method of  claim 12 , further comprising receiving a control signal to enable or disable the throttling regardless of whether the rate exceeded signal or the distress signal are asserted. 
     
     
         14 . The method of  claim 12 , further comprising using a leaky-bucket algorithm to determine whether to assert the rate exceeded signal. 
     
     
         15 . The method of  claim 12 , further comprising maintaining a request counter, the request counter to track how many requests are received in a time period. 
     
     
         16 . The method of  claim 15 , wherein the time period is a number of clock cycles. 
     
     
         17 . The method of  claim 16 , wherein the time period is measured using a time-window counter, the time-window counter configured to count down from a predetermined value at each clock cycle and cause the request counter to reset. 
     
     
         18 . The method of  claim 12 , further comprising not throttling response traffic to the traffic source. 
     
     
         19 . The method of  claim 12 , wherein throttling the memory traffic flow from the traffic source includes using a fixed throttle rate. 
     
     
         20 . The method of  claim 12 , wherein throttling the memory traffic flow from the traffic source includes using a variable throttle rate. 
     
     
         21 . The method of  claim 20 , wherein the variable throttle rate is a function of a number of active cores in a system. 
     
     
         22 . The method of  claim 12 , wherein the memory controller that interfaces with the memory device implements memory deduplication. 
     
     
         23 . At least one non-transitory machine-readable medium including instructions for computer memory management, the instructions when executed by a machine, cause the machine to perform the operations comprising:
 receiving a rate exceeded signal, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold:   receiving a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and   throttling the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.   
     
     
         24 . The machine-readable medium of  claim 23 , further comprising receiving a control signal to enable or disable the throttling regardless of whether the rate exceeded signal or the distress signal are asserted. 
     
     
         25 . The machine-readable medium of  claim 23 , further comprising using a leaky-bucket algorithm to determine whether to assert the rate exceeded signal.