Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit

Abstract

An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.

1 . An integrated circuit, including at least one vertical junction field-effect transistor, comprising:
 a semiconductor well of a first type of conductivity;   a drain region comprising a buried layer of the first type of conductivity having a doping level that is higher than a doping level of the semiconductor well;   a contact well of the first type of conductivity that extends from a surface of the semiconductor well down to the buried layer;   a gate region comprising two spaced apart first trenches in that are filled with a semiconductor material of a second type of conductivity, said two spaced apart first trenches bounding a channel region; and   a source region of the first type of conductivity on top of the semiconductor well at an active surface of the channel region.   
     
     
         2 . The integrated circuit according to  claim 1 , further comprising a field implantation region comprising two spaced apart second trenches that are filled with a semiconductor material of a second type of conductivity, said two spaced apart second trenches being separated from the two spaced apart first trenches by a portion of the semiconductor well. 
     
     
         3 . The integrated circuit according to  claim 2 , further comprising contact regions of the second type of conductivity on top of the semiconductor well, said contact regions making electrical contact to the semiconductor material of the second conductivity type present in the two spaced apart first trenches for the gate region and the two spaced apart second trenches of the field implantation region. 
     
     
         4 . The integrated circuit according to  claim 3 , further comprising an isolation region at the top of the semiconductor well for isolating the contact regions of the second type of conductivity from the source region of the first type of conductivity. 
     
     
         5 . The integrated circuit according to  claim 4 , wherein the isolation region is a LOCOS region. 
     
     
         6 . The integrated circuit according to  claim 4 , wherein the isolation region is a trench isolation region. 
     
     
         7 . The integrated circuit according to  claim 1 , further comprising contact regions of the second type of conductivity on top of the semiconductor well, said contact regions making electrical contact to the semiconductor material of the second conductivity type present in the two spaced apart first trenches for the gate region. 
     
     
         8 . The integrated circuit according to  claim 7 , further comprising an isolation region at the top of the semiconductor well for isolating the contact regions of the second type of conductivity from the source region of the first type of conductivity. 
     
     
         9 . The integrated circuit according to  claim 8 , wherein the isolation region is a LOCOS region. 
     
     
         10 . The integrated circuit according to  claim 8 , wherein the isolation region is a trench isolation region. 
     
     
         11 . The integrated circuit according to  claim 1 , wherein a distance between inner edges of the two spaced apart first trenches defines a critical dimension of the active surface of the channel region in contact with the source region of the first type of conductivity. 
     
     
         12 . The integrated circuit according to  claim 1 , further comprising at least one bipolar transistor of the first type of conductivity, at least one bipolar transistor of the second type of conductivity, at least one insulated-gate field-effect transistor of the first type of conductivity and at least one insulated-gate field-effect transistor of the second type of conductivity. 
     
     
         13 . The integrated circuit according to  claim 12 , wherein the buried layer and the contact well of the junction field-effect transistor are at a same level as buried layers and contact wells of collector regions of the bipolar transistor of the first type of conductivity and bipolar transistor of the second type of conductivity. 
     
     
         14 . The integrated circuit according to  claim 12 , wherein the gate region of the vertical junction field-effect transistor is at a same level as field implantation regions of the bipolar transistor of the first type of conductivity and bipolar transistor of the second type of conductivity. 
     
     
         15 . The integrated circuit according to  claim 12 , wherein the source region of the vertical junction field-effect transistor is at a same level as emitter regions of the bipolar transistor of the first type of conductivity and drain and source regions of insulated-gate field-effect transistor of the first type of conductivity. 
     
     
         16 . The integrated circuit according to  claim 12 , wherein the vertical junction field-effect transistor comprises gate contact regions of the second type of conductivity in contact with the gate regions, said gate contact regions at a same level as emitter regions of the bipolar transistor of the second type of conductivity and drain and source regions of the insulated-gate field-effect transistor of the second type of conductivity. 
     
     
         17 . The integrated circuit according to  claim 1 , wherein said at least one vertical junction field-effect transistor comprises a plurality of vertical junction field-effect transistors, wherein first ones of the plurality of vertical junction field-effect transistors have channel regions with critical dimensions of active surface different from second ones of the plurality of vertical junction field-effect transistors. 
     
     
         18 . The integrated circuit according to  claim 1 , wherein said at least one vertical junction field-effect transistor comprises a plurality of vertical junction field-effect transistors, wherein the plurality of vertical junction field-effect transistors form a cellular structure.