Gamma adjustment circuit and display driver circuit using the same

Abstract

A gamma adjustment circuit is provided. The gamma adjustment circuit includes: a first node; a second node different from the first node; a first decoder to which a first voltage signal and a second voltage signal are provided and which outputs either one of the first voltage signal and the second voltage signal as a third voltage signal; an amplifier which receives the third voltage signal as a positive input and outputs a fourth voltage signal; a second decoder which receives the fourth voltage signal and outputs the provided fourth voltage signal as a fifth voltage signal to one of the first and second nodes; a third decoder which is connected to the first and second nodes, receives the fifth voltage signal from one of the first and second nodes, and outputs the fifth voltage signal to a negative input terminal of the amplifier as a sixth voltage signal; and a first resistor connected between the first node and the second node.

1 . A gamma adjustment circuit comprising:
 a first decoder configured to receive a first voltage signal and a second voltage signal, and output one of the first voltage signal and the second voltage signal as a third voltage signal;   an amplifier including a positive input and a negative input, the positive input configured to receive the third voltage signal, and to output a fourth voltage signal;   a second decoder configured to output the fourth voltage signal to one of a first node and a second node as a fifth voltage signal;   a third decoder connected to the first node and the second node, the third decoder configured to output the fifth voltage signal to the negative input of the amplifier as a sixth voltage signal; and   a first resistor connected between the first node and the second node.   
     
     
         2 . The gamma adjustment circuit of  claim 1 , wherein the amplifier comprises:
 a cascaded differential amplifier connected to the positive input and the negative input such that the cascaded differential amplifier is configured to receive the third voltage signal from the first decoder via the positive input of the amplifier and the sixth voltage signal from the third decoder via the negative input of the amplifier;   a common source (CS) amplifier configured to output the fourth voltage signal to the second decoder.   
     
     
         3 . The gamma adjustment circuit of  claim 1 , further comprising:
 a first register connected to the first decoder such that the first decoder is configured to select one of the first and second voltage signals based on a value of the first register; and   a second register connected to the second decoder such that the second decoder is configured to select one of the first node and the second node based on a value from the second register.   
     
     
         4 . The gamma adjustment circuit of  claim 3 , wherein
 the second register is connected to the third decoder such that, based on the value from the second register, the third decoder is configured to select a same one of the first node and the second node as the second decoder.   
     
     
         5 . The gamma adjustment circuit of  claim 1 , further comprising:
 a second resistor connected between the second node and a third node, the second resistor having a same resistance as the first resistor, wherein
 the second decoder is configured to output the fourth voltage signal to one of the first node, the second node and the third node as the fifth voltage signal, and 
 the third decoder is configured to receive the fifth voltage signal from one of the first node, the second node and the third node, and to provide the fifth voltage signal to the negative input of the amplifier. 
   
     
     
         6 . The gamma adjustment circuit of  claim 1 , wherein magnitudes of voltage levels of the third voltage signal, the fifth voltage signal, and the sixth voltage signal are substantially equal. 
     
     
         7 . The gamma adjustment circuit of  claim 1 , wherein the first decoder,
 the second decoder, the third decoder and the amplifier are complementary metal-oxide semiconductors (CMOS).   
     
     
         8 . The gamma adjustment circuit of  claim 1 , wherein
 the first decoder is configured to determine a magnitude of an analog voltage, and   the second decoder is configured to determine which of the first node and the second node receive the analog voltage.   
     
     
         9 . A display driver circuit comprising:
 a source driver integrated circuit (IC) configured to transmit an analog voltage to a display panel;   a gate driver integrated circuit (IC) configured to control a gate of the display panel so that the analog voltage is provided to a storage device associated with the display panel;   a controller configured to control the source driver IC and the gate driver IC based on a signal received from a host; and   a gamma adjustment circuit configured to transmit the analog voltage to the source driver IC, the gamma adjustment circuit including,
 an amplifier including a cascade differential amplifier and a common source (CS) amplifier, the cascade differential amplifier configured to receive a first signal, and to generate a second signal based on the first signal, the CS amplifier configured to receive the second signal, and to generate a third signal based on the second signal, 
 a first decoder including a first output terminal and a second output terminal, the first decoder configured to receive the third signal from the CS amplifier, the first decoder configured to select, based on a first selection signal, one of the first output terminal and the second output terminal as a selected output terminal, to provide the third signal to the selected output terminal as a fourth signal, and 
 a second decoder including a first input terminal and a second input terminal. 
   
     
     
         10 . The display driver circuit of  claim 9 , wherein the second decoder is configured to receive the fourth signal, and to feedback the fourth signal to the cascade differential amplifier as a fifth signal. 
     
     
         11 . The display driver circuit of  claim 10 , wherein the second decoder is configured to select, based on a second section signal, one of the first input terminal and the second input terminal as a selected input terminal such that the selected input terminal of the second decoder is connected to the selected output terminal of the first decoder. 
     
     
         12 . The display driver circuit of  claim 9 , wherein
 the signal received from the host includes digital data,   the controller is configured to provide the digital data to the source driver IC, and   the source driver IC is configured to convert the digital data into the analog voltage, using the fourth signal.   
     
     
         13 . The display driver circuit of  claim 9 , wherein the gamma adjustment circuit further includes a third decoder configured to determine a magnitude of the first signal. 
     
     
         14 . The display driver circuit of  claim 13 , wherein the first decoder, the second decoder, the third decoder and the amplifier are complementary metal-oxide semiconductors (CMOS). 
     
     
         15 . A display driver circuit comprising:
 a source driver integrated circuit (IC) configured to transmit an analog voltage to a display panel;   a gate driver integrated circuit (IC) configured to control a gate of the display panel so that the analog voltage is provided to a storage device associated with the display panel;   a controller configured to control the source driver IC and the gate driver IC based on a signal received from a host; and   a gamma adjustment circuit configured to transmit the analog voltage to the source driver IC, the gamma adjustment circuit including,
 a first decoder including an input terminal and an output terminal, 
 a second decoder including an input terminal and an output terminal, the input terminal of the second decoder being connected, via at least a first node and a second node, to the output terminal of the first decoder, the first node and the second node having a first resistor connected therebetween, and 
 an amplifier including a negative input terminal, a positive input terminal and an output terminal, the negative input terminal of the amplifier being connected to the output terminal of the second decoder, and the output terminal of the amplifier being connected to the input terminal of the first decoder. 
   
     
     
         16 . The display driver circuit of  claim 15 , wherein
 the signal received from the host includes digital data,   the controller is configured to provide the digital data to the source driver IC, and   the source driver IC is configured to convert the digital data into the analog voltage, using the gamma adjustment circuit, and to transmit the analog voltage to the display panel.   
     
     
         17 . The display driver circuit of  claim 15 , wherein the gamma adjustment circuit further comprises:
 a third decoder connected to the positive input terminal of the amplifier, the third decoder configured to determine a first voltage to provide to the positive input terminal of the amplifier.   
     
     
         18 . The display driver circuit of  claim 17 , wherein the gamma adjustment circuit further comprises:
 a first register connected to the third decoder such that the third decoder is configured to determine the first voltage based on a value of the first register; and   a second register connected to the first decoder such that the first decoder is configured to select, based on a value of the second register, one of the first node and the second node as a selected node, and provide an output of the amplifier to the selected node as a second voltage.   
     
     
         19 . The display driver circuit of  claim 18 , wherein the second register is connected to the second decoder such that, based on the value of the second register, the first decoder and the second decoder are configured to select a same one of the first node and the second node as the selected node. 
     
     
         20 . The display driver circuit of  claim 17 , wherein the first decoder, the second decoder, the third decoder and the amplifier are complementary metal-oxide semiconductors (CMOS).