US2019294382A1PendingUtilityA1

Mass storage virtualization for cloud computing

Assignee: Sony Interactive Entertainment LLCPriority: Dec 19, 2013Filed: Jun 11, 2019Published: Sep 26, 2019
Est. expiryDec 19, 2033(~7.4 yrs left)· nominal 20-yr term from priority
A63F 13/352G06F 3/067G06F 13/28G06F 3/0605G06F 3/0604A63F 13/355G06F 3/0629H04L 67/1097A63F 13/95G06F 3/0664G06F 3/0655A63F 13/30
57
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Claims

Abstract

Aspects of the present disclosure relate to systems and methods for virtualizing mass storage using an interface card, or other special hardware unit, operatively coupled to a host system. In various implementations, the interface device and host system may collectively emulate a mass storage device for another “terminal” computing system in a manner that is transparent to the terminal system. Moreover, in various implementations, a mass storage device may be emulated in a manner that is transparent to the terminal system, without requiring modifications to the terminal platform's hardware or software architecture.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An interface device comprising:
 a first communication interface, the first communication interface being a mass storage interface;   a second communication interface, the second communication interface being an expansion interface; and   a specialized processing unit operatively coupled to said communication interfaces, the specialized processing unit having a mass storage device controller connected to the first communication interface and a memory access interface connected to the second communication interface,   wherein the mass storage device controller is configured to receive a mass storage data request through the first communication interface,   wherein the memory access interface is configured to notify a host system of the mass storage data request through the second communication interface.   
     
     
         2 . The interface device of  claim 1 ,
 further comprising a memory unit,   wherein the specialized processing unit includes a memory controller connected to the memory unit.   
     
     
         3 . The interface device of  claim 1 ,
 wherein the memory access interface is configured to notify the host system of the data request using an interrupt of the data request.   
     
     
         4 . The interface device of  claim 1 , wherein the memory access interface includes a DMA engine configured to implement data move operations. 
     
     
         5 . The interface device of  claim 1 ,
 wherein the specialized processing unit is a field programmable gate array (FPGA).   
     
     
         6 . The interface device of  claim 1 ,
 wherein the specialized processing unit is an application specific integrated circuit (ASIC).   
     
     
         7 . The interface device of  claim 1 , further comprising:
 a printed circuit board (PCB),   wherein the first communication interface includes one or more mass storage ports fixed to the PCB.   
     
     
         8 . The interface device of  claim 1 , further comprising:
 a printed circuit board (PCB),   wherein the second communication interface includes one or more expansion connectors fixed to the PCB.   
     
     
         9 . The interface device of  claim 1 ,
 wherein the first communication interface includes one or more mass storage ports,   wherein the specialized processing unit has a mass storage device controller for each said mass storage port.   
     
     
         10 . The interface device of  claim 1 ,
 wherein the first communication interface includes a plurality of mass storage ports,   wherein the specialized processing unit has plurality of mass storage device controllers,   wherein each said mass storage device controller is connected to a corresponding one of the mass storage ports.   
     
     
         11 . The interface device of  claim 1 ,
 wherein the first communication interface includes one or more serial Advanced Technology Attachment (SATA) ports,   wherein the specialized processing unit has a SATA device controller for each said SATA port.

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