Ferroelectric memory device

Abstract

A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a channel layer disposed on the semiconductor substrate, a ferroelectric layer disposed on the channel layer, and a gate electrode layer disposed on the ferroelectric layer. The channel layer includes an epitaxial film.

What is claimed is: 
     
         1 . A ferroelectric memory device comprising:
 a semiconductor substrate;   a channel layer disposed on the semiconductor substrate, the channel layer having an epitaxial film;   a ferroelectric layer disposed on the channel layer; and   a gate electrode layer disposed on the ferroelectric layer.   
     
     
         2 . The ferroelectric memory device of  claim 1 , wherein the ferroelectric layer contacts the channel layer. 
     
     
         3 . The ferroelectric memory device of  claim 1 , wherein the epitaxial film comprises silicon carbide (SiC) or silicon germanium (SiGe). 
     
     
         4 . The ferroelectric memory device of  claim 3 , wherein the epitaxial film is doped with an n-type dopant or a p-type dopant. 
     
     
         5 . The ferroelectric memory device of  claim 3 , wherein
 wherein a surface of the channel layer includes elemental carbon (C) of the silicon carbide or elemental germanium (Ge) of the silicon germanium.   
     
     
         6 . The ferroelectric memory device of  claim 3 , wherein the ferroelectric layer comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) and hafnium zirconium oxide (Hf 0.5 Zr 0.5 O 2 ). 
     
     
         7 . The ferroelectric memory device of  claim 6 , wherein the ferroelectric layer comprises at least one of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La) as a dopant. 
     
     
         8 . The ferroelectric memory device of  claim 1 , wherein the gate electrode layer comprises at least one selected from the group consisting of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and ruthenium oxide. 
     
     
         9 . The ferroelectric memory device of  claim 1 , further comprising:
 a source region and a drain region that are disposed in the semiconductor substrate at opposite ends of the gate electrode layer.   
     
     
         10 . A ferroelectric memory device comprising:
 a semiconductor substrate;   a threshold switching layer disposed on the semiconductor substrate;   a ferroelectric layer disposed on the threshold switching layer; and   a gate electrode layer disposed on the ferroelectric layer.   
     
     
         11 . The ferroelectric memory device of  claim 10 , further comprising:
 an interfacial insulation layer disposed between the semiconductor substrate and the threshold switching layer.   
     
     
         12 . The ferroelectric memory device of  claim 10 , wherein the threshold switching layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, hafnium oxide, tungsten oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, tantalum oxide, niobium oxide, and iron oxide. 
     
     
         13 . The ferroelectric memory device of  claim 12 , wherein the threshold switching layer comprises at least one of aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), copper (Cu), zirconium (Zr), hafnium (Hf), titanium (Ti), and nickel (Ni) as a dopant. 
     
     
         14 . The ferroelectric memory device of  claim 10 , wherein the interfacial insulation layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride. 
     
     
         15 . The ferroelectric memory device of  claim 10 , wherein the ferroelectric layer comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) and hafnium zirconium oxide (Hf 0.5 Zr 0.5 O 2 ). 
     
     
         16 . A ferroelectric memory device comprising:
 a semiconductor substrate;   a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface;   a plurality of resistor layers stacked vertically in the trench, each resistor layer having a different electrical resistance; and   a gate electrode layer electrically connected to each resistor layer in the plurality of resistor layers,   wherein the plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.   
     
     
         17 . The ferroelectric memory device of  claim 16 , further comprising:
 a source region and a drain region disposed in the fin structure at locations opposite to each other with respect to the trench.   
     
     
         18 . The ferroelectric memory device of  claim 16 , wherein each resistor layer of the plurality of resistor layers contacts a different portion of the ferroelectric layer along the sidewall surface of the trench. 
     
     
         19 . The ferroelectric memory device of  claim 16 , wherein each of the plurality of resistor layers comprises metal oxide having a different oxygen vacancy concentration. 
     
     
         20 . The ferroelectric memory device of  claim 19 , wherein the metal oxide comprises at least one of zirconium oxide, hafnium oxide, tungsten oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, tantalum oxide, niobium oxide and iron oxide. 
     
     
         21 . The ferroelectric memory device of  claim 16 , wherein the plurality of resistor layers are arranged to implement a gradient of electrical resistance. 
     
     
         22 . The ferroelectric memory device of  claim 16 , wherein the gate electrode layer contacts each resistor layer of the plurality of resistor layers inside the trench. 
     
     
         23 . The ferroelectric memory device of  claim 16 , wherein the ferroelectric layer comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) and hafnium zirconium oxide (Hf 0.5 Zr 0.5 O 2 ). 
     
     
         24 . The ferroelectric memory device of  claim 16 , further comprising:
 an interfacial insulation layer disposed between the ferroelectric layer and the fin structure,   wherein the interfacial insulation layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride.   
     
     
         25 . The ferroelectric memory device of  claim 24 , further comprising:
 a threshold switching layer disposed between the ferroelectric layer and the interfacial insulation layer,   wherein the threshold switching layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, hafnium oxide, tungsten oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, tantalum oxide, niobium oxide, and iron oxide.   
     
     
         26 . The ferroelectric memory device of  claim 16 , further comprising:
 a channel layer disposed between the ferroelectric layer and the fin structure and having an epitaxial film,   wherein the epitaxial film comprises silicon germanium (SiGe) or silicon carbide (SiC).   
     
     
         27 . The ferroelectric memory device of  claim 26 , wherein a surface of the channel layer includes elemental germanium (Ge) of the silicon germanium or elemental carbon (C) of the silicon carbide (SiC).