Electromagnetic radiation detector based on wafer bonding

Abstract

Monolithic pixel detectors, systems and methods for the detection and imaging of electromagnetic radiation with high spectral and spatial resolution comprise a Si wafer with a CMOS processed pixel readout bonded to an absorber wafer in wafer bonds comprising conducting bonds between doped, highly conducting charge collectors in the readout and highly conducting regions in the absorber wafer and poorly conducting bonds between regions of high resistivity.

1 . A monolithic CMOS integrated pixel detector for the detection of electromagnetic radiation configured for backside illumination, comprising a silicon readout wafer made from silicon of a first doping type, comprising CMOS pixel readout electronics processed in a thin silicon layer and including highly conducting doped regions of a second doping type acting as charge collectors spaced at a pixel size L, the charge collectors communicating with the readout electronics;
 said readout wafer being bonded by wafer bonds to an absorber wafer made from at least one single crystal semiconductor material, the absorber wafer further comprising highly conducting doped regions;   the pixel detector further comprising the readout wafer bonded, in an aligned manner, to the absorber wafer; wherein said wafer bonds comprise highly conducting bonds between the readout wafer and the absorber wafer and poorly conducting bonds between the readout wafer and the absorber wafer, the poorly conducting bonds having a resistance exceeding that of the highly conducting bonds at least by a factor of 10 2  thereby electrically isolating neighboring pixels so as to force charges generated in the absorber wafer to cross the conducting bonds and to be received by the charge collectors for processing by the pixel readout electronics when the detector is in operation.   
     
     
         2 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein the conducting bonds between the readout wafer and the absorber wafer are conducting covalent semiconductor bonds and wherein the poorly conducting bonds between the readout wafer and the absorber wafer are bonds between regions at least one of which is a highly resistive or insulating region or a p-n junction polarized in reverse direction when the detector is in operation, and wherein the poorly conducting bonds have a resistance exceeding that of the conducting covalent bonds at least by a factor selected from one of the group of ranges of factors consisting of 10 2 -10 4 , 10 4 -10 6  and 10 6 -10 8 . 
     
     
         3 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein the thin silicon layer has a thickness selected from one of the group of thicknesses consisting of 10-30 μm, 5-10 μm and 3-5 μm. 
     
     
         4 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein the highly conducting doped regions of the readout wafer and the highly conducting doped regions of the absorber wafer have a doping range selected from one of the group of doping ranges consisting of 1×10 18 -1×10 19  cm −3 , 1×10 19 -1×10 20  cm −3  and 1×10 20 -5×10 20 , cm −3 . 
     
     
         5 . The monolithic CMOS integrated pixel detector of  claim 1 , further including wafer alignment features aligning the readout wafer with the absorber wafer selected from one of the group of features consisting of wafer notches, wafer flats and alignment marks. 
     
     
         6 . The monolithic CMOS integrated pixel detector of  claim 1  adapted for the detection of infrared radiation. 
     
     
         7 . The monolithic CMOS integrated pixel detector of  claim 6 , wherein the pixel size L is in the range of 2-40 μm. 
     
     
         8 . The monolithic CMOS integrated pixel detector of  claim 7 , wherein the absorber wafer is pixelated in the form of absorber patches mutually isolated by insulating regions. 
     
     
         9 . The monolithic CMOS integrated pixel detector of  claim 8 , wherein the absorber patches are spaced by the pixel size L of the detector pixels. 
     
     
         10 . The monolithic CMOS integrated pixel detector of  claim 8 , wherein the absorber patches have a first width and the insulating regions have a second width, and wherein the sum of widths and is equal the pixel size L of the detector or a multiple thereof. 
     
     
         11 . The monolithic CMOS integrated pixel detector of  claim 7 , wherein highly resistive regions in the silicon readout wafer provide electrical isolation between neighboring pixels. 
     
     
         12 . The monolithic CMOS integrated pixel detector of  claim 7 , wherein the at least one single crystal semiconductor material of the absorber wafer is made of at least one of the group of materials consisting of Si, Ge, SiGe alloys, SiGeSn alloys, InAs, InGaAs alloys, InSb, the lead salts PbS, PbSe, PbTe and their alloys, and HgCdTe alloys. 
     
     
         13 . The monolithic CMOS integrated pixel detector of  claim 12 , wherein the at least one single crystal semiconductor material of the absorber wafer is made from an epitaxial wafer comprising at least one epitaxial layer on a single crystal substrate. 
     
     
         14 . The monolithic CMOS integrated pixel detector of  claim 13 , wherein the at least one epitaxial layer is a Ge, SiGe, SiGeSn, InGaAs, PbSeTe or HgCdTe alloy layer. 
     
     
         15 . The monolithic CMOS integrated pixel detector of  claim 12 , wherein the absorber wafer comprises a charge multiplication layer. 
     
     
         16 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein the silicon readout wafer comprises a charge multiplication layer. 
     
     
         17 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein an at least one alignment feature of the readout wafer is superimposed on an at least one alignment feature of the absorber wafer with the rotational misalignment of the two wafers kept within about 0.1 to 0.2 degrees, and the lateral displacement within about 200-400 μm. 
     
     
         18 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein an at least one alignment feature of the readout wafer is superimposed on an at least one alignment feature of the absorber wafer with the rotational misalignment of 200 mm wafers kept within about (2-5)×10 −4  degrees and the lateral misalignment within about 0.1-1 μm. 
     
     
         19 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein the second doping type is of an opposite doping type to that of the first doping type. 
     
     
         20 . The monolithic CMOS integrated pixel detector of  claim 1 , wherein the second doping type is of a similar doping type to that of the first doping type. 
     
     
         21 . A method for forming a monolithic CMOS integrated pixel detector for the detection of electromagnetic radiation, the method comprising
 a) providing a pixel readout electronics by CMOS processing of a silicon readout wafer;   b) forming highly conducting regions in the readout wafer spaced at a pixel size L acting as charge collectors and communicating with the pixel readout electronics;   c) forming at least one alignment feature in the readout wafer;   d) forming an absorber wafer from at least one single crystal semiconductor material;   e) forming highly conducting doped regions in the absorber wafer;   ff) forming at least one alignment feature in the absorber wafer;   g) bonding a carrier wafer to the CMOS stack of the readout wafer after planarizing the CMOS stack;   h) thinning and planarizing the readout wafer;   i) superimposing the at least one alignment feature of the readout wafer and the absorber wafer;   j) forming wafer bonds comprising highly conducting bonds and poorly conducting bonds between the readout wafer and the absorber wafer; wherein the poorly conducting bonds have a resistance exceeding that of the highly conducting bonds at least by at least 10 2 ; and   k) partially or completely removing the carrier wafer from the CMOS stack and opening bonding pads on the CMOS stack.   
     
     
         22 . The method of  claim 21 , wherein the forming of the highly conducting wafer bonds comprises forming covalent conducting bonds and wherein the forming of poorly conducting bonds between the readout wafer and the absorber wafer comprises forming bonds between regions at least one of which is a highly resistive or insulating region or forming bonds between semiconductor regions of opposite doping which become poorly conducting when the p-n junction is polarized in reverse direction during detector operation. 
     
     
         23 . The method of  claim 22 , wherein forming the absorber wafer comprises forming the absorber wafer in the form of absorber patches separated by insulating regions. 
     
     
         24 . The method of  claim 22 , wherein the forming of the absorber wafer from the at least one single crystal semiconductor material comprises forming an absorber wafer adapted for infrared detection from at least one material selected from one of the group of materials consisting of Si, Ge, SiGe alloys, SiGeSn alloys, InAs, InGaAs alloys, InSb, PbS, PbSe, PbTe, PbSeTe alloys and HgCdTe alloys. 
     
     
         25 . The method of  claim 24 , wherein forming the absorber wafer comprises forming at least one epitaxial layer on a single crystal substrate. 
     
     
         26 . The method of  claim 25 , wherein forming the at least one epitaxial layer on a single crystal substrate comprises forming the epitaxial layer on one substrate selected from one of the group of substrates consisting of Si, Ge, GaAs, InSb, CdTe and CdZnTe. 
     
     
         27 . The method of  claim 26 , wherein forming the absorber wafer with the at least one epitaxial layer on the single crystal substrate comprises steps of:
 a) providing a dielectric layer on the single crystal substrate;   b) opening windows in the dielectric layer consisting of first windows of narrower width extending to the single crystal substrate and second windows of wider width with dielectric sidewalls of a first height;   c) growing a first layer into first narrow windows and subsequently overgrowing the dielectric in the wider second windows to a second height by a selective epitaxy process;   d) growing a second layer in the wider second windows to a third height, such that the sum of the second height and third height is below the first height of the dielectric sidewalls of said windows;   e) growing a third layer in wider second windows with a faceted surface to a level above the dielectric sidewalls;   f) planarizing the faceted surface to remove the facets so as to generate a planar, smooth and essentially particle-free surface of the absorber wafer with a surface roughness of 0.3-0.5 nm or 0.1-0.3 nm, suitable for low temperature wafer bonding to a thinned CMOS processed readout wafer.   
     
     
         28 . The method of  claim 26 , wherein forming the absorber wafer with the at least one epitaxial layer on the single crystal substrate comprises the steps of:
 a) providing a patterned substrate for epitaxy in the form of pillars separated by trenches;   b) epitaxially growing SiGe alloy crystals with gaps on top of the pillars;   c) filling trenches and gaps between the SiGe crystals with insulating material; and   d) providing a flat and smooth surface with an RMS roughness below 0.5 nm or preferably about 0.1-0.3 nm of the absorber wafer by planarizing the surface of the SiGe alloy crystals by CMP to make it suitable for wafer bonding with a thinned CMOS processed readout wafer.   
     
     
         29 . The method of  claim 27 , wherein forming the at least one epitaxial layer comprises forming a charge multiplication layer. 
     
     
         30 . The method of  claim 28 , wherein forming the at least one epitaxial layer comprises forming a charge multiplication layer. 
     
     
         31 . The method of  claim 23 , wherein the CMOS processing of the readout wafer includes forming a charge multiplication layer. 
     
     
         32 . The method of  claim 25 , wherein forming the monolithic CMOS integrated pixel detector includes removing the single crystal substrate. 
     
     
         33 . The method of  claim 23 , wherein forming the monolithic CMOS integrated pixel detector further includes forming a metallic back contact. 
     
     
         34 . A detector made according to the method of  claim 21 , the detector having single photon detection capability when operated in Geiger mode. 
     
     
         35 . The detector of  claim 34 , wherein the absorber comprises an absorber region and an avalanche region made from a semiconductor with a larger bandgap than that of the absorber region, and wherein the avalanche region of the absorber communicates with the charge collectors of the readout wafer. 
     
     
         36 . The detector of  claim 34 , wherein the readout wafer comprises a Si avalanche region communicating with the charge collectors, and wherein the absorber comprises at least one semiconductor with a lower bandgap than that of the avalanche region. 
     
     
         37 . A device for non-destructive testing having the detector of  claim 1 , wherein the device includes:
 a) at least one switchable X-ray source with power supply   b) at least one X-ray detector communicating with readout unit,   c) one computerized control, data processing and display unit, one sample rotatable around at least one of the rotation axes,   
       wherein the power supply of the at least one X-ray source and the readout unit of the at least one X-ray detector communicate with and are synchronized by the computerized control, data processing and display unit controlling also the sample rotation in order to generate, process and display computed tomography images. 
     
     
         38 . A device for non-destructive testing having a plurality of the detectors of  claim 1 , wherein the device includes at least:
 a) one switchable X-ray source with power supply,   b) one array of X-ray detectors communicating with readout units,   c) one computerized control, data processing and display unit, and   d) data communication and control lines,   
       wherein the power supply of the at least one X-ray source and the readout units of the at least one array of X-ray detectors are interconnected by the communication and control lines and communicate with and are synchronized by the computerized control, data processing and display unit to generate, process and display computed tomography images. 
     
     
         39 . A vehicle equipped for assisted or autonomous driving having detectors of  claim 1 , wherein the equipment of the vehicle includes at least:
 a) an array of spatially separated infrared detectors communicating with readout units, and   b) data communications and power supply lines interconnecting all readout units and detectors to an on-board control and data processing center communicating with the data communications and power supply lines,   
       wherein the array of spatially separated and interconnected infrared detectors permits real time distance measurements from static and moving objects through triangulation.