Memory device and manufacturing methods thereof

Abstract

The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.

What is claimed is: 
     
         1 . A memory device comprising:
 a conductive layer;   a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction;   a semiconductor layer extending through the first electrode layers in the first direction;   a second electrode layer provided between the conductive layer and the first electrode layers; and   a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein   the semiconductor base has a first width at a portion thereof between extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and   the first width is greater than the second width.   
     
     
         2 . The memory device according to  claim 1 , further comprising:
 a first insulating film located between two adjacent first electrode layers spaced from each other in the first direction,   wherein end surfaces of the first insulating film facing the semiconductor layer are positioned, in a direction along the surface of the second electrode layer, at substantially the same location along the first direction as end surfaces of two of the first electrode layers contacting the semiconductor layer.   
     
     
         3 . The memory device according to  claim 1 , further comprising:
 a second insulating film provided between the semiconductor base and the second electrode layer, wherein the semiconductor base comprises silicon and the second insulating film comprises silicon oxide.   
     
     
         4 . The memory device according to  claim 1 , wherein the semiconductor base contacts the conductive layer. 
     
     
         5 . The memory device according to  claim 1 , wherein the end surfaces of the first electrode layers facing the semiconductor layer are aligned in the first direction. 
     
     
         6 . The memory device according to  claim 5 , wherein the end surface of the second electrode layer is recessed from the location of the end surfaces of the first electrode layers thereover. 
     
     
         7 . The memory device according to  claim 1 , wherein the semiconductor base extends inwardly of the conductive layer. 
     
     
         8 . The memory device according to  claim 1 , further comprising:
 a slit extending through the first and second electrodes in the first direction; and   an insulating base interposed between the slit and the conductive layer.   
     
     
         9 . A method of manufacturing a memory device, comprising:
 forming a stack of a plurality of alternating first insulating films and first sacrificial films on a conductive layer;   forming a memory hole penetrating the plurality of first insulating films and the plurality of sacrificial films extending to the conductive layer;   forming a plurality of recessed portions of the sacrificial films facing the inside the memory hole by selectively removing a portion of each of the plurality of sacrificial films facing the inside the memory hole;   forming a semiconductor base on top of the conductive layer inside the memory hole, the semiconductor base having an upper end positioned between a first of the first sacrificial film nearest to the conductive layer and a second of the first sacrificial film nearest to the first sacrificial film;   filling the recessed portions, other than the recessed portion closest to the conductive layer, in the memory hole;   forming a columnar semiconductor layer over the semiconductor base inside the memory hole;   forming a plurality of spaces between the plurality of first insulating films by selectively removing the plurality of first sacrificial films and material filling the recessed portions other than the recessed portion closest to the conductive layer;   forming a second insulating film by oxidizing a portion of the semiconductor base extending inwardly of the recessed portion closest to the conductive layer exposed to the space, among the plurality of spaces, closest to the conductive layer; and   forming an electrode layer in each of the plurality of spaces.   
     
     
         10 . The method according to  claim 9 , wherein filling the recessed portions, other than the recessed portion closest to the conductive layer, in the memory hole comprises depositing a second sacrificial film inwardly of the recessed portions and over the ends of the first insulting films exposed to the memory hole. 
     
     
         11 . The method according to  claim 10 , further comprising:
 removing the portion of the second sacrificial layer over the ends of the first insulting films exposed to the memory hole by anisotropic etching.   
     
     
         12 . The method according to  claim 11 , wherein the first and second sacrificial films comprise silicon nitride. 
     
     
         13 . The method according to  claim 9 , further comprising:
 forming a slit through the plurality of first insulating layers and first sacrificial layers and extending to the conductive layer at a location spaced from the memory hole; and   removing the first and second sacrificial layers by exposing the first and second sacrificial layers to an etchant supplied thereto through the slit.   
     
     
         14 . The method according to  claim 13 , further comprising:
 oxidizing the portion of the conductive layer exposed to the interior of the slit while oxidizing the a portion of the semiconductor base extending inwardly of the recessed portion closest to the conductive layer; and   removing the oxidized portion of the conductive layer before forming an electrode layer in each of the plurality of spaces.   
     
     
         15 . A method of manufacturing a memory device, comprising:
 forming a stack of a plurality of alternating first insulating films and sacrificial films on a conductive layer;   forming a memory hole penetrating the plurality of first insulating films and the plurality of sacrificial films and extending to the conductive layer;   forming a semiconductor base on top of the conductive layer inside the memory hole, the semiconductor base having an upper end positioned between a first sacrificial film, among the plurality of sacrificial films, nearest to the conductive layer and a second sacrificial film nearest to the first sacrificial film;   forming a columnar semiconductor layer within the memory hole and over the semiconductor base;   forming a plurality of spaces between the plurality of first insulating films by selectively removing the plurality of sacrificial films;   forming an extension on the sidewall of the semiconductor base and into the space nearest to the conductive layer;   forming a second insulating film by oxidizing at least a portion of the extension on the sidewall of the semiconductor base; and   forming an electrode layer in each of the plurality of spaces.   
     
     
         16 . The method according to  claim 15 , wherein, after the second insulating a film is formed, a portion of the extension on the sidewall of the semiconductor base remains extending inwardly of the space nearest to the conductive layer. 
     
     
         17 . The method according to  claim 15 , wherein the semiconductor base and the extending portion comprise silicon. 
     
     
         18 . The method according to  claim 15 , wherein the semiconductor base is epitaxially grown on a portion of the conductive layer exposed to the memory hole, and the extending portion is epitaxially grown on the semiconductor base. 
     
     
         19 . The method according to  claim 15 , further comprising:
 forming a slit through the plurality of alternating first insulating films and first sacrificial films on the conductive layer extending to the conductive layer.   
     
     
         20 . The method according to  claim 19 , further comprising:
 forming a semiconductor layer on the conductive layer exposed to the slit while forming the extension on the sidewall of the semiconductor base.