Semiconductor memory device

Abstract

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

1 .- 24 . (canceled) 
     
     
         25 . A semiconductor memory device, comprising:
 a substrate that includes active regions defined by a device isolation layer;   word line structures filling trenches formed in an upper portion of the substrate, the word line structures intersecting the active regions to divide the active regions into first dopant regions and second dopant regions;   bit lines intersecting the word line structures, the bit lines being connected to the first dopant regions; and   data storage parts connected to the second dopant regions,   wherein each of the word line structures includes a word line, a capping pattern, and a remaining pattern, which are sequentially stacked in each of the trenches.   
     
     
         26 . The semiconductor memory device as claimed in  claim 25 , wherein the remaining pattern extends along a top surface of the word line. 
     
     
         27 . The semiconductor memory device as claimed in  claim 25 , further comprising a buffer pattern between the substrate and the bit lines, wherein a top surface of the remaining pattern is in contact with a bottom surface of the buffer pattern. 
     
     
         28 . The semiconductor memory device as claimed in  claim 27 , further comprising first contacts connecting the bit lines to the first dopant regions, wherein the first contacts penetrate the buffer pattern so as to be connected to the remaining pattern. 
     
     
         29 . The semiconductor memory device as claimed in  claim 28 , wherein each of bottom surfaces of the first contacts is higher than a top surface of the capping pattern. 
     
     
         30 . The semiconductor memory device as claimed in  claim 28 , wherein each of bottom surfaces of the first contacts is lower than a bottom surface of the remaining pattern. 
     
     
         31 . The semiconductor memory device as claimed in  claim 27 , further comprising an interlayer insulating layer covering side surfaces of the bit lines, wherein the interlayer insulating layer penetrates the buffer pattern so as to be connected to the device isolation layer. 
     
     
         32 . The semiconductor memory device as claimed in  claim 27 , wherein the buffer pattern comprises a first buffer pattern and a second buffer pattern, the first buffer pattern and the second buffer pattern are formed of different materials. 
     
     
         33 . The semiconductor memory device as claimed in  claim 25 , wherein the remaining pattern comprises a stepwise structure including a side surface and a bottom surface. 
     
     
         34 . The semiconductor memory device as claimed in  claim 33 , further comprising a first contact connecting each of the bit lines to the first dopant regions, wherein the bottom surface of the stepwise structure contacts a bottom surface of the first contact. 
     
     
         35 . The semiconductor memory device as claimed in  claim 25 , wherein a width of the remaining pattern decreases from a top surface of the remaining pattern to a bottom surface of the remaining pattern. 
     
     
         36 . The semiconductor memory device as claimed in  claim 25 , wherein a side surface of the remaining pattern aligns with a side surface of the capping pattern. 
     
     
         37 . The semiconductor memory device as claimed in  claim 25 , wherein a bottom surface of the remaining pattern is higher than bottom surfaces of the first dopant regions. 
     
     
         38 . A semiconductor memory device, comprising:
 a substrate that includes active regions defined by a device isolation layer;   a word line structure filling a trench formed in an upper portion of the substrate, the word line structure intersecting the active regions to divide the active regions into a first dopant region and a second dopant region;   a bit line intersecting the word line structure, the bit line being connected to the first dopant region;   a buffer pattern between the substrate and the bit lines; and   a first contact connecting the bit line to the first dopant region,   wherein the word line structure includes a word line, a capping pattern, and a remaining pattern, which are sequentially stacked in the trench, and   the first contacts penetrate the buffer pattern so as to be connected to the remaining pattern.   
     
     
         39 . The semiconductor memory device as claimed in  claim 38 , wherein a bottom surface of the first contact is higher than a top surface of the capping pattern. 
     
     
         40 . The semiconductor memory device as claimed in  claim 38 , wherein the remaining pattern comprises a stepwise structure including a side surface and a bottom surface, the bottom surface of the stepwise structure contacts a bottom surface of the first contact. 
     
     
         41 . The semiconductor memory device as claimed in  claim 38 , wherein the remaining pattern extends along a top surface of the word line. 
     
     
         42 . A semiconductor memory device, comprising:
 a substrate that includes active regions defined by a device isolation layer;   word line structures filling trenches formed in an upper portion of the substrate, the word line structures intersecting the active regions to divide the active regions into first dopant regions and second dopant regions;   bit lines intersecting the word line structures, the bit lines being connected to the first dopant regions;   a first contact connecting the bit line to the first dopant region; and   data storage parts connected to the second dopant regions,   wherein each of the word line structures includes a word line, a capping pattern, and a remaining pattern, which are sequentially stacked in each of the trenches, and   the remaining pattern comprises a stepwise structure connected to a bottom portion of the first contact.   
     
     
         43 . The semiconductor memory device as claimed in  claim 42 , wherein the remaining pattern extends along a top surface of the word line. 
     
     
         44 . The semiconductor memory device as claimed in  claim 42 , wherein a bottom surface of the first contact is higher than a top surface of the capping pattern.