Multi-use package architecture

Abstract

A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

We claim: 
     
         1 . A semiconductor package comprising:
 a substrate;   one or more dies on a first side of the substrate;   a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate, the interconnect structures to attach the substrate to a board,
 wherein the substrate comprises a first interconnect layer having a second pitch, wherein the first interconnect layer is coupled to the one or more dies through second one or more interconnect layers, wherein third one or more interconnect layers between the first interconnect layer and the interconnect structures are to translate the first pitch to the second pitch, and wherein the substrate comprises a recess on a section of the second side of the substrate; and 
   one or more components within the recess and attached to the second side of the substrate at the second pitch.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the one or more components are attached to the first interconnect layer at the second pitch. 
     
     
         3 . The semiconductor package of  claim 1 , further comprising:
 a structure comprising metal embedded within a portion of the substrate extending laterally beyond an edge of the dies, the metal electrically isolated from the first, second, and third interconnect layers.   
     
     
         4 . The semiconductor package of  claim 3 , wherein the structure comprises a plurality of layers of the metal, individual features comprising the metal interconnected over the layers, and wherein the structure is adjacent to at least two sides of the die. 
     
     
         5 . The semiconductor package of  claim 4 , wherein the structure comprises:
 a first layer that is coplanar with a layer of the second one or more interconnect layers;   a second layer that is coplanar with another layer of the second one or more interconnect layers; and   a third layer that interconnects the first and second layers.   
     
     
         6 . The semiconductor package of  claim 3 , wherein at least some portion of the structure is electrically coupled to the die and to at least one of the interconnect structures. 
     
     
         7 . The semiconductor package of  claim 3 , wherein no portion of the structure is electrically coupled to the die or any of the interconnect structures. 
     
     
         8 . The semiconductor package of  claim 1 , wherein the first pitch is larger than the second pitch. 
     
     
         9 . The semiconductor package of  claim 7 , wherein:
 the first pitch is in the range of 0.60 to 0.70 millimeter (mm); and   the second pitch is in the range of 0.40 to 0.50 mm.   
     
     
         10 . The semiconductor package of  claim 1 , wherein the one or more components comprises one or more of: a capacitor, or an inductor. 
     
     
         11 . A system comprising:
 a memory to store instructions;   a processor coupled to the memory;   a die comprising at least one of the memory or the processor;   a substrate, wherein the die is disposed on a first side of the substrate;   a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate, to attach the substrate to a board,   wherein the substrate comprises a first interconnect layer having a second pitch, wherein the first interconnect layer is coupled to the one or more dies through second one or more interconnect layers, wherein third one or more interconnect layers between the first interconnect layer and the interconnect structures are to translate the first pitch to the second pitch, wherein the substrate comprises a recess on a section of the second side of the substrate; and   one or more components attached to the second side of the substrate through the recess at the second pitch.   
     
     
         12 . The system of  claim 1 , further comprising:
 a structure comprising metal embedded within a portion of the substrate extending laterally beyond an edge of the die, the metal electrically isolated from the first, second, and third interconnect layers.   
     
     
         13 . The system of  claim 11 , wherein the one or more components comprises one or more of: a capacitor, or a magnetic inductor. 
     
     
         14 . The system of  claim 11 , wherein the first pitch is different from the second pitch. 
     
     
         15 . A method comprising:
 forming a coreless substrate on a carrier, wherein the substrate comprises a sacrificial layer, and wherein forming the coreless substrate comprises:
 forming a first interconnect layer with a first pitch and a second interconnect layer with a second pitch, such that the first interconnect layer is embedded within the substrate, and 
 forming one or more pitch translation layers between the first interconnect layer and the second interconnect layer; 
   stripping the sacrificial layer to form a recess within the substrate, the recess exposing at least a part of the first interconnect layer; and   attaching one or more components through the recess to the first interconnect layer.   
     
     
         16 . The method of  claim 15 , further comprising:
 attaching a plurality of interconnect structures having the second pitch to the second interconnect layer.   
     
     
         17 . The method of  claim 15 , further comprising:
 attaching a die to the substrate, the die coupled to the first interconnect layer via one or more intervening interconnect layers.   
     
     
         18 . The method of  claim 17 , wherein forming the coreless substrate further comprises:
 forming a structure comprising metal, the structure embedded within the substrate and electrically isolated from the first and second interconnect layers, wherein forming the structure comprises:
 forming a first layer of the structure to be coplanar with one of the one or more intervening interconnect layers; and 
 forming a second layer of the structure to be orthogonal to the first layer. 
   
     
     
         19 . The method of  claim 15 , wherein:
 the one or more pitch translation layers are to translate the first pitch of the first interconnect layer to the second pitch of the second interconnect layer.   
     
     
         20 . The method of  claim 15 , further comprising:
 detaching the substrate from the carrier.