Substrate with a fin region comprising a stepped height structure

Abstract

A method of forming a semiconductor structure includes forming a fin region and a non-fin region surrounding the fin region in a substrate, wherein sidewalls of the fin region comprise a stepped height structure comprising an outer portion adjacent to the non-fin region with a first height and an inner portion with a second height greater than the first height. The method also includes forming a plurality of fins disposed over a top surface of the inner portion of the fin region, forming an isolation layer disposed over the top surface of the inner portion of the fin region surrounding a portion of the sidewalls of the plurality of fins, and forming a fin liner disposed (i) between the isolation layer and the top surface of the inner portion of the fin region and (ii) between the isolation layer and the portion of the sidewalls of the plurality of fins.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate comprising a fin region and a non-fin region surrounding the tin region, wherein sidewalls of the fin region comprise a stepped height structure comprising an outer portion adjacent to the non-fin region with a first height and an inner portion with a second height greater than the first height;   a plurality of fins disposed over a top surface of the inner portion of the fin region;   an isolation layer disposed over the top surface of the inner portion of the tin region surrounding a portion of the sidewalls of the plurality of fins; and   a fin liner disposed (i) between the isolation layer and the top surface of the inner portion of the fin region and (ii) between the isolation layer and the portion of the sidewalls of the plurality of fins.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the plurality of fins have uniform channel dimension. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the fin liner comprises vertical portions disposed in the isolation layer over the stepped height structure. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the isolation layer is further disposed over the top surface of the substrate in the non-fin region, and wherein the fin liner is further disposed between the isolation layer and the top surface of the substrate in the non-fin region. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the isolation layer comprises silicon oxide (SiO). 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the fin liner comprises silicon nitride (SiN). 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the fin liner has a thickness in the range of about 3 to 10 nanometers (nm). 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the fin liner is further disposed on (iii) a top surface of the stepped height structure. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the fin liner is further disposed (iii) vertically extending from a top surface of the substrate at the outer portion adjacent the non-fin region and (iv) vertically extending from the top surface of the substrate at the inner portion adjacent the fin region. 
     
     
         10 . The semiconductor structure of  claim 1 , further comprising:
 a gate dielectric disposed over a portion of the plurality of fins and the isolation layer in the fin region;   a gate conductor disposed over the gate dielectric;   a gate spacer surrounding the gate dielectric and the gate conductor; and   source/drain regions disposed over the top surface of the substrate in the fin region surrounding the gate spacer.   
     
     
         11 . An integrated circuit comprising:
 a fin field-effect transistor (FinFET) device comprising:
 a substrate comprising a fin region and a non-fin region surrounding the fin region, wherein sidewalk of the fin region comprise a stepped height structure comprising an outer portion adjacent to the non-fin region with a first height and an inner portion with a second height greater than the first height; 
 a plurality of fins disposed over a top surface of the inner portion of the fin region; 
 an isolation layer disposed over the top surface of the inner portion of the fin region surrounding a portion of the sidewalls of the plurality of fins; and 
   a fin liner disposed (i) between the isolation layer and the top surface of the inner portion of the fin region and (ii) between the isolation layer and the portion of the sidewalls of the plurality of fins.   
     
     
         12 . The integrated circuit of  claim 11 , wherein the plurality of fins have uniform channel dimension. 
     
     
         13 . The integrated circuit of  claim 11 , wherein the fin liner comprises vertical portions disposed in the isolation layer over the stepped height structure. 
     
     
         14 . The integrated circuit of  claim 11 , wherein the isolation layer is further disposed over the top surface of the substrate in the non-fin region, and wherein the fin liner is further disposed between the isolation layer and the top surface of the substrate in the non-fin region. 
     
     
         15 . The integrated circuit of claim therein the isolation layer comprises silicon oxide (SiO). 
     
     
         16 . The integrated circuit of  claim 15 , wherein the fin liner comprises silicon nitride (SiN). 
     
     
         17 . The integrated circuit of  claim 11 , wherein the fin liner has a thickness in the range of about 3 to 10 nanometers (nm). 
     
     
         18 . The integrated circuit of  claim 11 , wherein the fin liner is further disposed on (iii) a top surface of the stepped height structure. 
     
     
         19 . The integrated circuit of  claim 11 , wherein the fin liner is further disposed (iii) vertically extending from a top surface of the substrate at the outer portion adjacent the non-fin region and (iv) vertically extending from the top surface of the substrate at the inner portion adjacent the fin region. 
     
     
         20 . The integrated circuit of  claim 11 , wherein the FinFET device further comprises:
 a gate dielectric disposed over a portion of the plurality of fins and the isolation layer in the fin region;   a gate conductor disposed over the gate dielectric;   a gate spacer surrounding the gate dielectric and the gate conductor; and   source/drain regions disposed over the top surface of the substrate in the fin region surrounding the gate spacer.