Cpld cache application in a multi-master topology system

Abstract

An example multi-node system that prevents multi-master issues on a common bus is disclosed. The system has a first node and a second node. A backplane is coupled to the first and second nodes via a system management bus. A complex programmable logic device is coupled to the system management bus. The complex programmable logic device includes hardware logic operable to arbitrate between bus commands from the first and second nodes.

1 . A system, comprising:
 a first node;   a second node;   a backplane coupled to the first and second nodes via a system management bus;   a power supply unit coupled to the backplane via a power management bus; and   a complex programmable logic device coupled to the system management bus, the complex programmable logic device including hardware logic operable to arbitrate between bus commands from the first and second nodes, the complex programmable logic device configured to select a bus command from one of the first and second nodes, and pass along the bus command to the power supply unit.   
     
     
         2 . The system of  claim 1 , wherein the system management bus operates with an I2C protocol. 
     
     
         3 . (canceled) 
     
     
         4 . The system of  claim 1 , wherein the complex programmable logic device includes a memory that includes power management commands, wherein the complex programmable logic device is operable to receive performance data from the power supply unit via the power management bus. 
     
     
         5 . The system of  claim 4 , wherein the nodes are operable to obtain performance data of the power supply unit by sending a request to the complex programmable logic device. 
     
     
         6 . The system of  claim 1 , wherein at least one of the first and second nodes includes a baseboard management controller coupled to the system management bus. 
     
     
         7 . A method of arbitrating commands between two nodes coupled via a system management bus to a backplane, the method comprising:
 coupling a complex programmable logic device to the system management bus;   receiving a first command from a first node via the system management bus;   receiving a second command from a second node via the system management bus; and   operating hardware logic of the complex programmable logic device to arbitrate whether the first or the second node constitutes a master for the system management bus, and pass along select a bus command from one of the first and second nodes, and pass along the bus command to a power supply unit.   
     
     
         8 . The method of  claim 7 , wherein the system management bus operates with an I2C protocol. 
     
     
         9 . The method of  claim 7 , wherein the power supply unit is coupled to the backplane via a power management bus. 
     
     
         10 . The method of  claim 9 , wherein the complex programmable logic device includes a memory that includes power management commands, the method further comprising the complex programmable logic device receiving performance data from the power supply unit via the power management bus. 
     
     
         11 . The method of  claim 10 , further comprising the first node sending a request to the complex programmable logic device for the performance data. 
     
     
         12 . The method of  claim 7 , wherein at least one of the first and second nodes includes a baseboard management controller coupled to the system management bus.