US2019283206A1PendingUtilityA1
Polishing pad, semiconductor fabricating device and fabricating method of semiconductor device
Est. expiryMar 13, 2038(~11.6 yrs left)· nominal 20-yr term from priority
H10P 95/064H10P 52/403H10W 20/4441H10W 20/0698H10W 20/092H10W 20/083H10W 20/062H10P 95/062B24B 53/017B24B 37/24B24B 37/26H01L 21/76895H01L 21/76805H01L 21/31055H01L 23/53257H01L 21/3212H01L 21/76819H01L 21/7684
53
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A polishing pad for polishing a substrate, comprising
a surface for polishing the substrate, the surface including a plurality of recess portions; wherein an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm 2 or more.
2 . The polishing pad according to claim 1 , wherein
the polishing pad has an elastic modulus of 4.0×10 8 Pa or more at a temperature of 30° C., and an elastic modulus of 2.0×10 8 Pa or more at 60° C.
3 . The polishing pad according to claim 1 , wherein
the polishing pad has a Shore hardness of 50 or more and 65 or less.
4 . The polishing pad according to claim 1 , wherein
the average width of the recess portions at the one area of the surface in the direction parallel to the surface is 10 μm or more.
5 . The polishing pad according to claim 1 , wherein
a shape of the recess portions in the surface is a circular shape, an elliptic shape, or a polygonal shape.
6 . The polishing pad according to claim 1 , wherein
a shape of the recess portions in the surface is a triangular shape or a quadrangular shape.
7 . The polishing pad according to claim 1 , wherein
the recess portions are formed by using at least one of dry etching, wet etching, a balloon, a foaming agent, cutting, a wire discharge, a laser, or a die.
8 . A semiconductor fabricating device comprising:
a polishing table which holds a polishing pad which includes a surface having plural recess portions, and in which an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm 2 or more; a polishing liquid supply configured to supply a polishing liquid to the surface of the polishing pad; and a polishing head configured to rotate a substrate that is polished by the surface of the polishing pad.
9 . The semiconductor fabricating device according to claim 8 , further comprising:
a dresser arranged to perform a dressing of an upper surface of the polishing pad.
10 . The semiconductor fabricating device according to claim 8 , wherein the average width of the recess portions at the one area of the surface in the direction parallel to the surface is 10 μm or more.
11 . The semiconductor fabricating device according to claim 8 , further comprising:
a temperature adjuster configured to adjust a surface temperature of the polishing pad.
12 . The semiconductor fabricating device according to claim 11 , wherein
the temperature adjuster is configured to:
adjust a surface temperature of the polishing pad to a first temperature in a first step of polishing the substrate, and
adjust the surface temperature of the polishing pad to a second temperature lower than the first temperature in a second step of polishing the substrate after the first step.
13 . The semiconductor fabricating device according to claim 12 , wherein the temperature adjuster is configured to adjust the surface temperature of the polishing pad such that the first step is performed at a higher polishing rate than that in the second step.
14 . The semiconductor fabricating device according to claim 12 , wherein the temperature adjuster is configured to adjust the surface temperature of the polishing pad such that the second step increases a flatness of the substrate compared to the first step.
15 . A fabricating method of a semiconductor device, the method comprising:
holding, by a polishing table, a polishing pad which includes a surface having plural recess portions, wherein an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm 2 or more; supplying a polishing liquid to the surface of the polishing pad; and polishing the substrate using the surface of the polishing pad.
16 . The method according to claim 15 , wherein the average width of the recess portions at the one area of the surface in the direction parallel to the surface is 10 μm or more.
17 . The method of claim 15 , further comprising:
dressing an upper surface of the polishing pad before and after the polishing the substrate.
18 . The method of claim 15 , wherein the step of polishing comprising:
a first step of polishing in which a surface temperature of the polishing pad is at a first temperature, and a second step of polishing in which the surface temperature of the polishing pad is changed to a second temperature different from the first temperature.
19 . The method of claim 18 , wherein first step of polishing is performed at a higher polishing rate than the second step of polishing.
20 . The method of claim 18 , wherein second step of polishing increase a flatness of the substrate compared to the first step of polishing.Join the waitlist — get patent alerts
Track US2019283206A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.